bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / pifploadshift.mdwn

diff --git a/openpower/isa/pifploadshift.mdwn b/openpower/isa/pifploadshift.mdwn
index 281ec28079fd7963fcb2302a6f8217bce6da63ed..b6853842cda0dfabb81c9abdf590535c86934d3c 100644 (file)
--- a/openpower/isa/pifploadshift.mdwn
+++ b/openpower/isa/pifploadshift.mdwn
@@ -1,22 +1,22 @@
-<!-- X Instructions here described in PowerISA Version 3.0 B Book 1 -->
+<!-- https://bugs.libre-soc.org/show_bug.cgi?id=1055 -->
+<!-- https://libre-soc.org/openpower/sv/rfc/ls004/ -->
 
-<!-- Section 4.6.1 Floating-point storage access instructions. P 140 - 143 -->
+# Load Floating-Point Single with Post-Update Shifted Indexed
 
-# Load Floating-Point Single with Post-Update Indexed
+Z23-Form
 
-X-Form
-
-* lfsupx FRT,RA,RB
+* lfsupsx FRT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB)<<(SH+1)
     FRT <- DOUBLE(MEM(RA, 4))
     RA <- EA
 
 Description:
 
-    Let the effective address (EA) be the sum (RA)+(RB).
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and the contents of register RA.
 
     The word in storage addressed by EA is interpreted as
     a floating-point single-precision operand. This word is
@@ -33,19 +33,20 @@ Special Registers Altered:
 
 # Load Floating-Point Double with Post-Update Indexed
 
-X-Form
+Z23-Form
 
-* lfduxp FRT,RA,RB
+* lfdupsx FRT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB)<<(SH+1)
     FRT <- MEM(RA, 8)
     RA <- EA
 
 Description:
 
-    Let the effective address (EA) be the sum (RA)+(RB).
+    Let the effective address (EA) be the sum of the contents of
+    register RB shifted by (SH+1), and the contents of register RA.
 
     The doubleword in storage addressed by EA is loaded
     into register FRT.