bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / sprset.mdwn

diff --git a/openpower/isa/sprset.mdwn b/openpower/isa/sprset.mdwn
index ab1ace714a17c28871969ff11854800888e1c49f..61454907549ff93c311ee52a8ae1f2a38bd02757 100644 (file)
--- a/openpower/isa/sprset.mdwn
+++ b/openpower/isa/sprset.mdwn
@@ -31,11 +31,11 @@
 
 XFX-Form
 
-* mtspr SPR,RS
+* mtspr spr,RS
 
 Pseudo-code:
 
-    n <- spr[5:9] || spr[0:4]
+    n <- spr
     switch (n)
       case(13): see(Book_III_p974)
       case(808, 809, 810, 811):
@@ -55,11 +55,11 @@ Special Registers Altered:
 
 XFX-Form
 
-* mfspr RT,SPR
+* mfspr RT,spr
 
 Pseudo-code:
 
-    n <- spr[5:9] || spr[0:4]
+    n <- spr
     switch (n)
       case(129): see(Book_III_p975)
       case(808, 809, 810, 811):
@@ -175,6 +175,62 @@ Special Registers Altered:
 
     None
 
+# Set Boolean Condition
+
+X-Form
+
+* setbc RT,BI
+
+Pseudo-code:
+
+    RT <- (CR[BI + 32] = 1) ? 1 : 0
+
+Special Registers Altered:
+
+    None
+
+# Set Boolean Condition Reverse
+
+X-Form
+
+* setbcr RT,BI
+
+Pseudo-code:
+
+    RT <- (CR[BI + 32] = 1) ? 0 : 1
+
+Special Registers Altered:
+
+    None
+
+# Set Negative Boolean Condition
+
+X-Form
+
+* setnbc RT,BI
+
+Pseudo-code:
+
+    RT <- (CR[BI + 32] = 1) ? -1 : 0
+
+Special Registers Altered:
+
+    None
+
+# Set Negative Boolean Condition Reverse
+
+X-Form
+
+* setnbcr RT,BI
+
+Pseudo-code:
+
+    RT <- (CR[BI + 32] = 1) ? 0 : -1
+
+Special Registers Altered:
+
+    None
+
 <!-- Out of order from the PDF. Page 977 -->
 
 # Move To Machine State Register