bug #1183: attempt first ddffirst mapreduce mode

[openpower-isa.git] / openpower / isa / svbranch.mdwn

diff --git a/openpower/isa/svbranch.mdwn b/openpower/isa/svbranch.mdwn
index 0c15a04d6725d57beabc734a32e922bc9d3a1ff8..e8b46e7700b44c6112ee2d873cc2e04b3c732370 100644 (file)
--- a/openpower/isa/svbranch.mdwn
+++ b/openpower/isa/svbranch.mdwn
@@ -46,23 +46,34 @@ Pseudo-code:
         testbit = SNZ
     else
         testbit <- CR[BI+32]
+    # test CTR mode here
+    if (mode_is_64bit) then M <- 0
+    else M <- 32
+    if ¬BO[2] then CTR <- CTR - 1
+    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
     # actual element test here
     cond_ok <- BO[0] | ¬(testbit ^ BO[1])
     # test for VL to be set (and exit)
-    if VLSET & (cond_ok = VSb) then
+    if VLSET & ((cond_ok & ctr_ok) = VSb) then
         if VLI then
             SVSTATE[7:13] <- (srcstep+1)
         else
-            SVSTATE[7:13] <- srcstep+1
+            SVSTATE[7:13] <- srcstep
+        end_loop <- 0b1
     # XXX if svstep_mode then
     # XXX   SVSTATE.srcstep = new_srcstep
     # actual branch
-    if (mode_is_64bit) then M <- 0
-    else M <- 32
-    if ¬BO[2] then CTR <- CTR - 1
-    ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3])
+    test_branch <- 0b1
+    if ALL then
+        # in ALL mode only try branching at end of loop
+        if ¬end_loop then
+            test_branch <- 0b0
+        # test early-exit. ALL will exit if cond_ok fails
+        if ¬(cond_ok & ctr_ok) then
+            end_loop <- 0b1
+            test_branch <- 0b0
     lr_ok <- LRu
-    if ctr_ok & cond_ok then
+    if test_branch & ctr_ok & cond_ok then
       if AA then NIA <-iea EXTS(BD || 0b00)
       else       NIA <-iea CIA + EXTS(BD || 0b00)
       lr_ok <- 0b1