add comment/header on ld/st shift instructions

[openpower-isa.git] / openpower / isa / svfixedarith.mdwn

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index c7050133f2eae8c4d9d8f864a07621f046dc2158..6ce79fb69925bef2faef666c0a251e860ec3e3b0 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -18,6 +18,32 @@ Special Registers Altered:
 
     None
 
+# [DRAFT] Multiply and Add Extended Doubleword Unsigned Signed
+
+VA-Form
+
+* maddedus RT,RA,RB,RC
+
+Pseudo-code:
+
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
+    <!-- no MULUS, so do it manually -->
+    prod[0:XLEN*2-1] <- [0] * (XLEN * 2)
+    if (RB)[0] != 0 then
+        prod[0:XLEN*2-1] <- -((RA) * -(RB))
+    else
+        prod[0:XLEN*2-1] <- (RA) * (RB)
+    <!-- no EXTS2XL, so do it manually -->
+    sum[0:XLEN*2-1] <- prod + (EXTSXL((RC)[0], 1) || (RC))
+    RT <- sum[XLEN:2*XLEN-1]
+    RS <- sum[0:XLEN-1]
+
+Special Registers Altered:
+
+    None
+
 # [DRAFT] Divide/Modulo Double-width Doubleword Unsigned
 
 VA-Form
@@ -44,7 +70,7 @@ Pseudo-code:
 
 Special Registers Altered:
 
-    None
+    XER.OV
 
 # [DRAFT] Double-width Shift Left Doubleword
 
@@ -60,9 +86,9 @@ Pseudo-code:
     mask <- MASK(0, 63-n)
     RT <- (v[0:63] & mask) | ((RC) & ¬mask)
     RS <- v[0:63] & ¬mask
-    overflow <- 0
+    overflow <- 0             # relevant only when Rc=1
     if RS != [0]*64 then
-        overflow <- 1
+        overflow <- 1         # relevant only when Rc=1
 
 Special Registers Altered:
 
@@ -82,9 +108,9 @@ Pseudo-code:
     mask <- MASK(n, 63)
     RT <- (v[0:63] & mask) | ((RC) & ¬mask)
     RS <- v[0:63] & ¬mask
-    overflow <- 0
+    overflow <- 0             # relevant only when Rc=1
     if RS != [0]*64 then
-        overflow <- 1
+        overflow <- 1         # relevant only when Rc=1
 
 Special Registers Altered: