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[openpower-isa.git] / openpower / isa / svfixedarith.mdwn

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index 0888f5fbc770ca08133b82ae7a3dd2c833208ce7..6ce79fb69925bef2faef666c0a251e860ec3e3b0 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -1,4 +1,4 @@
-# [DRAFT] Multiply and Add Extended Doubleword
+# [DRAFT] Multiply and Add Extended Doubleword Unsigned
 
 VA-Form
 
@@ -9,10 +9,36 @@ Pseudo-code:
     <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
     <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
     <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
-    prod[0:127] <- (RA) * (RB)
-    sum[0:127] <- ([0] * 64 || (RC)) + prod
-    RT <- sum[64:127]
-    RS <- sum[0:63]
+    prod[0:2*XLEN-1] <- (RA) * (RB)
+    sum[0:2*XLEN-1] <- ([0] * XLEN || (RC)) + prod
+    RT <- sum[XLEN:2*XLEN-1]
+    RS <- sum[0:XLEN-1]
+
+Special Registers Altered:
+
+    None
+
+# [DRAFT] Multiply and Add Extended Doubleword Unsigned Signed
+
+VA-Form
+
+* maddedus RT,RA,RB,RC
+
+Pseudo-code:
+
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
+    <!-- no MULUS, so do it manually -->
+    prod[0:XLEN*2-1] <- [0] * (XLEN * 2)
+    if (RB)[0] != 0 then
+        prod[0:XLEN*2-1] <- -((RA) * -(RB))
+    else
+        prod[0:XLEN*2-1] <- (RA) * (RB)
+    <!-- no EXTS2XL, so do it manually -->
+    sum[0:XLEN*2-1] <- prod + (EXTSXL((RC)[0], 1) || (RC))
+    RT <- sum[XLEN:2*XLEN-1]
+    RS <- sum[0:XLEN-1]
 
 Special Registers Altered:
 
@@ -44,38 +70,25 @@ Pseudo-code:
 
 Special Registers Altered:
 
-    None
+    XER.OV
 
 # [DRAFT] Double-width Shift Left Doubleword
 
-Z23-Form
+VA2-Form
 
-* dsld    RT,RA,RB,sm  (Rc=0)
-* dsld.   RT,RA,RB,sm  (Rc=1)
+* dsld    RT,RA,RB,RC  (Rc=0)
+* dsld.   RT,RA,RB,RC  (Rc=1)
 
 Pseudo-code:
 
-    switch(sm)
-        case(0):
-            hi <- (RT)
-            lo <- (RA)
-            sh <- (RB)
-        case(1):
-            hi <- (RA)
-            lo <- (RT)
-            sh <- (RB)
-        case(2):
-            hi <- (RA)
-            lo <- (RB)
-            sh <- (RT)
-        default:
-            hi <- [0] * 64
-            lo <- (RA)
-            sh <- (RB)
-    n <- sh[58:63]
-    mask[0:63] <- MASK(n, 63)
-    v[0:63] <- (hi & mask) | (lo & ¬mask)
-    RT <- ROTL64(v, n)
+    n <- (RB)[58:63]
+    v <- ROTL64((RA), n)
+    mask <- MASK(0, 63-n)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
+    overflow <- 0             # relevant only when Rc=1
+    if RS != [0]*64 then
+        overflow <- 1         # relevant only when Rc=1
 
 Special Registers Altered:
 
@@ -83,34 +96,21 @@ Special Registers Altered:
 
 # [DRAFT] Double-width Shift Right Doubleword
 
-Z23-Form
+VA2-Form
 
-* dsrd    RT,RA,RB,sm  (Rc=0)
-* dsrd.   RT,RA,RB,sm  (Rc=1)
+* dsrd    RT,RA,RB,RC  (Rc=0)
+* dsrd.   RT,RA,RB,RC  (Rc=1)
 
 Pseudo-code:
 
-    switch(sm)
-        case(0):
-            hi <- (RT)
-            lo <- (RA)
-            sh <- (RB)
-        case(1):
-            hi <- (RA)
-            lo <- (RT)
-            sh <- (RB)
-        case(2):
-            hi <- (RA)
-            lo <- (RB)
-            sh <- (RT)
-        default:
-            hi <- (RA)
-            lo <- [0] * 64
-            sh <- (RB)
-    n <- sh[58:63]
-    mask[0:63] <- MASK(0, 63 - n)
-    v[0:63] <- (hi & ¬mask) | (lo & mask)
-    RT <- ROTL64(v, 64 - n)
+    n <- (RB)[58:63]
+    v <- ROTL64((RA), 64-n)
+    mask <- MASK(n, 63)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
+    overflow <- 0             # relevant only when Rc=1
+    if RS != [0]*64 then
+        overflow <- 1         # relevant only when Rc=1
 
 Special Registers Altered: