Pseudo-code:
- # SVP64: RA,RB,RC,RT have EXTRA2, RS as below
- # bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
- # bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v]
+ <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+ <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
+ <!-- bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v]
prod[0:127] <- (RA) * (RB)
sum[0:127] <- EXTZ(RC) + prod
RT <- sum[64:127]
Pseudo-code:
- # SVP64: RA,RB,RC,RT have EXTRA2, RS as below
- # bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL
- # bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v]
+ <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+ <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
+ <!-- bit 8 of EXTRA is set : RS.[s|v]=RC.[s|v]
if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
dividend[0:(XLEN*2)-1] <- (RC) || (RA)
divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)