use widths.get(dw/sw) and test empty/non-empty after.

[openpower-isa.git] / openpower / isa / svfixedarith.mdwn

diff --git a/openpower/isa/svfixedarith.mdwn b/openpower/isa/svfixedarith.mdwn
index ebef59cea55e4934c1d4c3becb5e14019d51ea25..7dfd4c551a82962f53446b678ac58d7b95970cbd 100644 (file)
--- a/openpower/isa/svfixedarith.mdwn
+++ b/openpower/isa/svfixedarith.mdwn
@@ -6,9 +6,9 @@ VA-Form
 
 Pseudo-code:
 
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- EXTZ(RC) + prod
     RT <- sum[64:127]
@@ -18,7 +18,7 @@ Special Registers Altered:
 
     None
 
-# [DRAFT] Twin Divide Quad Unsigned
+# [DRAFT] Twin Divide/Modulo Quad Unsigned
 
 VA-Form
 
@@ -26,11 +26,11 @@ VA-Form
 
 Pseudo-code:
 
-    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below   -->
-    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+VL -->
-    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]    -->
-    if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
-        dividend[0:(XLEN*2)-1] <- (RA) || (RC)
+    <!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
+    <!-- bit 8 of EXTRA is clear: RS.[s|v]=RT.[s|v]+MAXVL
+    <!-- bit 8 of EXTRA is set  : RS.[s|v]=RC.[s|v]
+    if ((RC) <u (RB)) & ((RB) != [0]*XLEN) then
+        dividend[0:(XLEN*2)-1] <- (RC) || (RA)
         divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
         result <- dividend / divisor
         modulo <- dividend % divisor