<!-- SVP64: RA,RB,RC,RT have EXTRA2, RS as below
<!-- bit 8 of EXTRA is set : RS.[s|v]=RT.[s|v]+MAXVL
<!-- bit 8 of EXTRA is clear: RS.[s|v]=RC.[s|v]
- prod[0:127] <- (RA) * (RB)
- sum[0:127] <- ([0] * 64 || (RC)) + prod
- RT <- sum[64:127]
- RS <- sum[0:63]
+ prod[0:2*XLEN-1] <- (RA) * (RB)
+ sum[0:2*XLEN-1] <- ([0] * XLEN || (RC)) + prod
+ RT <- sum[XLEN:2*XLEN-1]
+ RS <- sum[0:XLEN-1]
Special Registers Altered: