use widths.get(dw/sw) and test empty/non-empty after.

[openpower-isa.git] / openpower / isa / svfparith.mdwn

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
index 1bcc1ac7f653b0ffecbc439a28f611df0c555acf..a7b05457b701941979e672a4d9a6a4cc20601302 100644 (file)
--- a/openpower/isa/svfparith.mdwn
+++ b/openpower/isa/svfparith.mdwn
@@ -5,7 +5,9 @@
 <!-- FRS is automatically calculated by SVP64 to FRT+VL (default elwidth) -->
 <!-- (Vector FRS data sequentially starts immediately after FRT vectors) -->
 
-# Floating Add FFT/DCT [Single]
+<!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
+
+# [DRAFT] Floating Add FFT/DCT [Single]
 
 A-Form
 
@@ -15,7 +17,7 @@ A-Form
 Pseudo-code:
 
     FRT <- FPADD32(FRA, FRB)
-    FRS <- FPSUB32(FRA, FRB)
+    FRS <- FPSUB32(FRB, FRA)
 
 Special Registers Altered:
 
@@ -24,7 +26,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Add FFT/DCT [Double]
+# [DRAFT] Floating Add FFT/DCT [Double]
 
 A-Form
 
@@ -34,7 +36,7 @@ A-Form
 Pseudo-code:
 
     FRT <- FPADD64(FRA, FRB)
-    FRS <- FPSUB64(FRA, FRB)
+    FRS <- FPSUB64(FRB, FRA)
 
 Special Registers Altered:
 
@@ -43,7 +45,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Subtract FFT/DCT [Single]
+# [DRAFT] Floating Subtract FFT/DCT [Single]
 
 A-Form
 
@@ -52,7 +54,7 @@ A-Form
 
 Pseudo-code:
 
-    FRT <- FPSUB32(FRA, FRB)
+    FRT <- FPSUB32(FRB, FRA)
     FRS <- FPADD32(FRA, FRB)
 
 Special Registers Altered:
@@ -62,7 +64,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Subtract FFT/DCT [Double]
+# [DRAFT] Floating Subtract FFT/DCT [Double]
 
 A-Form
 
@@ -71,7 +73,7 @@ A-Form
 
 Pseudo-code:
 
-    FRT <- FPSUB64(FRA, FRB)
+    FRT <- FPSUB64(FRB, FRA)
     FRS <- FPADD64(FRA, FRB)
 
 Special Registers Altered:
@@ -81,7 +83,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply FFT/DCT [Single]
+# [DRAFT] Floating Multiply FFT/DCT [Single]
 
 A-Form
 
@@ -100,7 +102,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply FFT/DCT [Double]
+# [DRAFT] Floating Multiply FFT/DCT [Double]
 
 A-Form
 
@@ -119,7 +121,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Divide FFT/DCT [Single]
+# [DRAFT] Floating Divide FFT/DCT [Single]
 
 A-Form
 
@@ -138,7 +140,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Divide FFT/DCT [Double]
+# [DRAFT] Floating Divide FFT/DCT [Double]
 
 A-Form
 
@@ -157,7 +159,27 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply-Add FFT/DCT [Single]
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
+
+A-Form
+
+* fdmadds FRT,FRA,FRC,FRB (Rc=0)
+* fdmadds. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+    FRS <- FPADD32(FRA, FRB)
+    sub <- FPSUB32(FRA, FRB)
+    FRT <- FPMUL32(FRC, sub)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)
+
+# [DRAFT] Floating Multiply-Add FFT [Single]
 
 A-Form
 
@@ -176,7 +198,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Multiply-Sub FFT/DCT [Single]
+# [DRAFT] Floating Multiply-Sub FFT [Single]
 
 A-Form
 
@@ -195,7 +217,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Negative Multiply-Add FFT/DCT [Single]
+# [DRAFT] Floating Negative Multiply-Add FFT [Single]
 
 A-Form
 
@@ -214,7 +236,7 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Negative Multiply-Sub FFT/DCT [Single]
+# [DRAFT] Floating Negative Multiply-Sub FFT [Single]
 
 A-Form
 
@@ -232,4 +254,3 @@ Special Registers Altered:
     FX OX UX XX
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
-