<!-- SVP64 FP Instructions here described are based on -->
<!-- PowerISA Version 3.0 B Book 1 -->
-# Floating Add FFT/DCT [Single]
+<!-- FRS in each of these does not need to be explicitly declared -->
+<!-- FRS is automatically calculated by SVP64 to FRT+VL (default elwidth) -->
+<!-- (Vector FRS data sequentially starts immediately after FRT vectors) -->
+
+<!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
+
+# [DRAFT] Floating Add FFT/DCT [Single]
A-Form
-* faddso FRT,FRA,FRB (Rc=0)
-* faddso. FRT,FRA,FRB (Rc=1)
+* ffadds FRT,FRA,FRB (Rc=0)
+* ffadds. FRT,FRA,FRB (Rc=1)
Pseudo-code:
FRT <- FPADD32(FRA, FRB)
- FRS <- FPSUB32(FRA, FRB)
+ FRS <- FPSUB32(FRB, FRA)
Special Registers Altered:
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Add FFT/DCT [Double]
+# [DRAFT] Floating Add FFT/DCT [Double]
A-Form
-* faddo FRT,FRA,FRB (Rc=0)
-* faddo. FRT,FRA,FRB (Rc=1)
+* ffadd FRT,FRA,FRB (Rc=0)
+* ffadd. FRT,FRA,FRB (Rc=1)
Pseudo-code:
FRT <- FPADD64(FRA, FRB)
- FRS <- FPSUB64(FRA, FRB)
+ FRS <- FPSUB64(FRB, FRA)
Special Registers Altered:
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Subtract FFT/DCT [Single]
+# [DRAFT] Floating Subtract FFT/DCT [Single]
A-Form
-* fsubso FRT,FRA,FRB (Rc=0)
-* fsubso. FRT,FRA,FRB (Rc=1)
+* ffsubs FRT,FRA,FRB (Rc=0)
+* ffsubs. FRT,FRA,FRB (Rc=1)
Pseudo-code:
- FRT <- FPSUB32(FRA, FRB)
+ FRT <- FPSUB32(FRB, FRA)
FRS <- FPADD32(FRA, FRB)
Special Registers Altered:
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Subtract FFT/DCT [Double]
+# [DRAFT] Floating Subtract FFT/DCT [Double]
A-Form
-* fsubo FRT,FRA,FRB (Rc=0)
-* fsubo. FRT,FRA,FRB (Rc=1)
+* ffsub FRT,FRA,FRB (Rc=0)
+* ffsub. FRT,FRA,FRB (Rc=1)
Pseudo-code:
- FRT <- FPSUB64(FRA, FRB)
+ FRT <- FPSUB64(FRB, FRA)
FRS <- FPADD64(FRA, FRB)
Special Registers Altered:
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Multiply FFT/DCT [Single]
+# [DRAFT] Floating Multiply FFT/DCT [Single]
A-Form
-* fmulso FRT,FRA,FRC (Rc=0)
-* fmulso. FRT,FRA,FRC (Rc=1)
+* ffmuls FRT,FRA,FRC (Rc=0)
+* ffmuls. FRT,FRA,FRC (Rc=1)
Pseudo-code:
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Multiply FFT/DCT [Double]
+# [DRAFT] Floating Multiply FFT/DCT [Double]
A-Form
-* fmulo FRT,FRA,FRC (Rc=0)
-* fmulo. FRT,FRA,FRC (Rc=1)
+* ffmul FRT,FRA,FRC (Rc=0)
+* ffmul. FRT,FRA,FRC (Rc=1)
Pseudo-code:
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Divide FFT/DCT [Single]
+# [DRAFT] Floating Divide FFT/DCT [Single]
A-Form
-* fdivso FRT,FRA,FRB (Rc=0)
-* fdivso. FRT,FRA,FRB (Rc=1)
+* ffdivs FRT,FRA,FRB (Rc=0)
+* ffdivs. FRT,FRA,FRB (Rc=1)
Pseudo-code:
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Divide FFT/DCT [Double]
+# [DRAFT] Floating Divide FFT/DCT [Double]
A-Form
-* fdivo FRT,FRA,FRB (Rc=0)
-* fdivo. FRT,FRA,FRB (Rc=1)
+* ffdiv FRT,FRA,FRB (Rc=0)
+* ffdiv. FRT,FRA,FRB (Rc=1)
Pseudo-code:
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Multiply-Add FFT/DCT [Single]
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
+
+A-Form
+
+* fdmadds FRT,FRA,FRC,FRB (Rc=0)
+* fdmadds. FRT,FRA,FRC,FRB (Rc=1)
+
+Pseudo-code:
+
+ FRS <- FPADD32(FRA, FRB)
+ sub <- FPSUB32(FRA, FRB)
+ FRT <- FPMUL32(FRC, sub)
+
+Special Registers Altered:
+
+ FPRF FR FI
+ FX OX UX XX
+ VXSNAN VXISI VXIMZ
+ CR1 (if Rc=1)
+
+# [DRAFT] Floating Multiply-Add FFT [Single]
A-Form
-* fmaddso FRT,FRA,FRC,FRB (Rc=0)
-* fmaddso. FRT,FRA,FRC,FRB (Rc=1)
+* ffmadds FRT,FRA,FRC,FRB (Rc=0)
+* ffmadds. FRT,FRA,FRC,FRB (Rc=1)
Pseudo-code:
FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
- FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
+ FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
Special Registers Altered:
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-# Floating Multiply-Sub FFT/DCT [Single]
+# [DRAFT] Floating Multiply-Sub FFT [Single]
A-Form
-* fmsubso FRT,FRA,FRC,FRB (Rc=0)
-* fmsubso. FRT,FRA,FRC,FRB (Rc=1)
+* ffmsubs FRT,FRA,FRC,FRB (Rc=0)
+* ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
Pseudo-code:
FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
- FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
+ FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
Special Registers Altered:
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-# Floating Negative Multiply-Add FFT/DCT [Single]
+# [DRAFT] Floating Negative Multiply-Add FFT [Single]
A-Form
-* fnmaddso FRT,FRA,FRC,FRB (Rc=0)
-* fnmaddso. FRT,FRA,FRC,FRB (Rc=1)
+* ffnmadds FRT,FRA,FRC,FRB (Rc=0)
+* ffnmadds. FRT,FRA,FRC,FRB (Rc=1)
Pseudo-code:
FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
- FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+ FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
Special Registers Altered:
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-# Floating Negative Multiply-Sub FFT/DCT [Single]
+# [DRAFT] Floating Negative Multiply-Sub FFT [Single]
A-Form
-* fnmsubso FRT,FRA,FRC,FRB (Rc=0)
-* fnmsubso. FRT,FRA,FRC,FRB (Rc=1)
+* ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
+* ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)
Pseudo-code:
FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
- FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+ FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
Special Registers Altered:
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-