missing colon on end of "Description"

[openpower-isa.git] / openpower / isa / svfparith.mdwn

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
index bebb3be45f86dc2c6a0de36d24f84aff0a5359bb..b6066f8fb2715ab71af6f6a5d172a501feee9572 100644 (file)
--- a/openpower/isa/svfparith.mdwn
+++ b/openpower/isa/svfparith.mdwn
@@ -7,7 +7,7 @@
 
 <!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
 
-# Floating Add FFT/DCT [Single]
+# [DRAFT] Floating Add FFT/DCT [Single]
 
 A-Form
 
@@ -26,7 +26,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Add FFT/DCT [Double]
+# [DRAFT] Floating Add FFT/DCT [Double]
 
 A-Form
 
@@ -45,7 +45,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Subtract FFT/DCT [Single]
+# [DRAFT] Floating Subtract FFT/DCT [Single]
 
 A-Form
 
@@ -64,7 +64,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Subtract FFT/DCT [Double]
+# [DRAFT] Floating Subtract FFT/DCT [Double]
 
 A-Form
 
@@ -83,7 +83,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply FFT/DCT [Single]
+# [DRAFT] Floating Multiply FFT/DCT [Single]
 
 A-Form
 
@@ -102,7 +102,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply FFT/DCT [Double]
+# [DRAFT] Floating Multiply FFT/DCT [Double]
 
 A-Form
 
@@ -121,7 +121,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Divide FFT/DCT [Single]
+# [DRAFT] Floating Divide FFT/DCT [Single]
 
 A-Form
 
@@ -140,7 +140,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Divide FFT/DCT [Double]
+# [DRAFT] Floating Divide FFT/DCT [Double]
 
 A-Form
 
@@ -159,17 +159,18 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Twin Multiply-Add DCT [Single]
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
 
-A-Form
+DCT-Form
 
-* fdmadds FRT,FRA,FRC,FRB (Rc=0)
-* fdmadds. FRT,FRA,FRC,FRB (Rc=1)
+* fdmadds FRT,FRA,FRB (Rc=0)
+* fdmadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPADD32(FRA, FRB)
-    FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+    FRS <- FPADD32(FRT, FRB)
+    sub <- FPSUB32(FRT, FRB)
+    FRT <- FPMUL32(FRA, sub)
 
 Special Registers Altered:
 
@@ -178,17 +179,18 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Multiply-Add FFT [Single]
+# [DRAFT] Floating Multiply-Add FFT [Single]
 
 A-Form
 
-* ffmadds FRT,FRA,FRC,FRB (Rc=0)
-* ffmadds. FRT,FRA,FRC,FRB (Rc=1)
+* ffmadds FRT,FRA,FRB (Rc=0)
+* ffmadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, 1, 1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, -1, 1)
 
 Special Registers Altered:
 
@@ -197,17 +199,18 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Multiply-Sub FFT [Single]
+# [DRAFT] Floating Multiply-Sub FFT [Single]
 
 A-Form
 
-* ffmsubs FRT,FRA,FRC,FRB (Rc=0)
-* ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
+* ffmsubs FRT,FRA,FRB (Rc=0)
+* ffmsubs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, 1, -1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, -1, -1)
 
 Special Registers Altered:
 
@@ -216,17 +219,18 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Negative Multiply-Add FFT [Single]
+# [DRAFT] Floating Negative Multiply-Add FFT [Single]
 
 A-Form
 
-* ffnmadds FRT,FRA,FRC,FRB (Rc=0)
-* ffnmadds. FRT,FRA,FRC,FRB (Rc=1)
+* ffnmadds FRT,FRA,FRB (Rc=0)
+* ffnmadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, -1, -1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, 1, -1)
 
 Special Registers Altered:
 
@@ -235,35 +239,18 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Negative Multiply-Sub FFT [Single]
+# [DRAFT] Floating Negative Multiply-Sub FFT [Single]
 
 A-Form
 
-* ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
-* ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-
-# Floating SIN [Single]
-
-X-Form
-
-* fsins FRT,FRB (Rc=0)
-* fsins. FRT,FRB (Rc=1)
+* ffnmsubs FRT,FRA,FRB (Rc=0)
+* ffnmsubs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPSIN32(FRB)
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, -1, 1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, 1, 1)
 
 Special Registers Altered:
 
@@ -271,22 +258,3 @@ Special Registers Altered:
     FX OX UX XX
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
-
-# Floating COS [Single]
-
-X-Form
-
-* fcoss FRT,FRB (Rc=0)
-* fcoss. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
-    FRT <- FPCOS32(FRB)
-
-Special Registers Altered:
-
-    FPRF FR FI
-    FX OX UX XX
-    VXSNAN VXISI VXIMZ
-    CR1          (if Rc=1)
-