<!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
-# Floating Add FFT/DCT [Single]
+# [DRAFT] Floating Add FFT/DCT [Single]
A-Form
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Add FFT/DCT [Double]
+# [DRAFT] Floating Add FFT/DCT [Double]
A-Form
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Subtract FFT/DCT [Single]
+# [DRAFT] Floating Subtract FFT/DCT [Single]
A-Form
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Subtract FFT/DCT [Double]
+# [DRAFT] Floating Subtract FFT/DCT [Double]
A-Form
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Multiply FFT/DCT [Single]
+# [DRAFT] Floating Multiply FFT/DCT [Single]
A-Form
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Multiply FFT/DCT [Double]
+# [DRAFT] Floating Multiply FFT/DCT [Double]
A-Form
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Divide FFT/DCT [Single]
+# [DRAFT] Floating Divide FFT/DCT [Single]
A-Form
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Divide FFT/DCT [Double]
+# [DRAFT] Floating Divide FFT/DCT [Double]
A-Form
VXSNAN VXISI
CR1 (if Rc=1)
-# Floating Twin Multiply-Add DCT [Single]
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
-A-Form
+DCT-Form
-* fdmadds FRT,FRA,FRC,FRB (Rc=0)
-* fdmadds. FRT,FRA,FRC,FRB (Rc=1)
+* fdmadds FRT,FRA,FRB (Rc=0)
+* fdmadds. FRT,FRA,FRB (Rc=1)
Pseudo-code:
- FRT <- FPADD32(FRA, FRB)
- sub <- FPSUB32(FRB, FRA)
- FRS <- FPMUL32(FRC, sub)
+ FRS <- FPADD32(FRT, FRB)
+ sub <- FPSUB32(FRT, FRB)
+ FRT <- FPMUL32(FRA, sub)
Special Registers Altered:
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-# Floating Multiply-Add FFT [Single]
+# [DRAFT] Floating Multiply-Add FFT [Single]
A-Form
-* ffmadds FRT,FRA,FRC,FRB (Rc=0)
-* ffmadds. FRT,FRA,FRC,FRB (Rc=1)
+* ffmadds FRT,FRA,FRB (Rc=0)
+* ffmadds. FRT,FRA,FRB (Rc=1)
Pseudo-code:
- FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
- FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+ tmp <- FRT
+ FRT <- FPMULADD32(tmp, FRA, FRB, 1, 1)
+ FRS <- FPMULADD32(tmp, FRA, FRB, -1, 1)
Special Registers Altered:
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-# Floating Multiply-Sub FFT [Single]
+# [DRAFT] Floating Multiply-Sub FFT [Single]
A-Form
-* ffmsubs FRT,FRA,FRC,FRB (Rc=0)
-* ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
+* ffmsubs FRT,FRA,FRB (Rc=0)
+* ffmsubs. FRT,FRA,FRB (Rc=1)
Pseudo-code:
- FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
- FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+ tmp <- FRT
+ FRT <- FPMULADD32(tmp, FRA, FRB, 1, -1)
+ FRS <- FPMULADD32(tmp, FRA, FRB, -1, -1)
Special Registers Altered:
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-# Floating Negative Multiply-Add FFT [Single]
+# [DRAFT] Floating Negative Multiply-Add FFT [Single]
A-Form
-* ffnmadds FRT,FRA,FRC,FRB (Rc=0)
-* ffnmadds. FRT,FRA,FRC,FRB (Rc=1)
+* ffnmadds FRT,FRA,FRB (Rc=0)
+* ffnmadds. FRT,FRA,FRB (Rc=1)
Pseudo-code:
- FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
- FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
+ tmp <- FRT
+ FRT <- FPMULADD32(tmp, FRA, FRB, -1, -1)
+ FRS <- FPMULADD32(tmp, FRA, FRB, 1, -1)
Special Registers Altered:
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-# Floating Negative Multiply-Sub FFT [Single]
+# [DRAFT] Floating Negative Multiply-Sub FFT [Single]
A-Form
-* ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
-* ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)
-
-Pseudo-code:
-
- FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
- FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
-
-Special Registers Altered:
-
- FPRF FR FI
- FX OX UX XX
- VXSNAN VXISI VXIMZ
- CR1 (if Rc=1)
-
-# Floating SIN [Single]
-
-X-Form
-
-* fsins FRT,FRB (Rc=0)
-* fsins. FRT,FRB (Rc=1)
+* ffnmsubs FRT,FRA,FRB (Rc=0)
+* ffnmsubs. FRT,FRA,FRB (Rc=1)
Pseudo-code:
- FRT <- FPSIN32(FRB)
+ tmp <- FRT
+ FRT <- FPMULADD32(tmp, FRA, FRB, -1, 1)
+ FRS <- FPMULADD32(tmp, FRA, FRB, 1, 1)
Special Registers Altered:
FX OX UX XX
VXSNAN VXISI VXIMZ
CR1 (if Rc=1)
-
-# Floating COS [Single]
-
-X-Form
-
-* fcoss FRT,FRB (Rc=0)
-* fcoss. FRT,FRB (Rc=1)
-
-Pseudo-code:
-
- FRT <- FPCOS32(FRB)
-
-Special Registers Altered:
-
- FPRF FR FI
- FX OX UX XX
- VXSNAN VXISI VXIMZ
- CR1 (if Rc=1)
-