added stdsx instruction

[openpower-isa.git] / openpower / isa / svfparith.mdwn

diff --git a/openpower/isa/svfparith.mdwn b/openpower/isa/svfparith.mdwn
index 021a7c3d1d9c8a13872ee38d7769b05a9e1d8b5b..b6066f8fb2715ab71af6f6a5d172a501feee9572 100644 (file)
--- a/openpower/isa/svfparith.mdwn
+++ b/openpower/isa/svfparith.mdwn
@@ -5,7 +5,9 @@
 <!-- FRS is automatically calculated by SVP64 to FRT+VL (default elwidth) -->
 <!-- (Vector FRS data sequentially starts immediately after FRT vectors) -->
 
-# Floating Add FFT/DCT [Single]
+<!-- PLEASE NOTE THESE ARE UNAPPROVED AND DRAFT, NOT SUBMITTED TO OPF ISA WG -->
+
+# [DRAFT] Floating Add FFT/DCT [Single]
 
 A-Form
 
@@ -24,7 +26,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Add FFT/DCT [Double]
+# [DRAFT] Floating Add FFT/DCT [Double]
 
 A-Form
 
@@ -43,7 +45,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Subtract FFT/DCT [Single]
+# [DRAFT] Floating Subtract FFT/DCT [Single]
 
 A-Form
 
@@ -62,7 +64,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Subtract FFT/DCT [Double]
+# [DRAFT] Floating Subtract FFT/DCT [Double]
 
 A-Form
 
@@ -81,7 +83,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply FFT/DCT [Single]
+# [DRAFT] Floating Multiply FFT/DCT [Single]
 
 A-Form
 
@@ -100,7 +102,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply FFT/DCT [Double]
+# [DRAFT] Floating Multiply FFT/DCT [Double]
 
 A-Form
 
@@ -119,7 +121,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Divide FFT/DCT [Single]
+# [DRAFT] Floating Divide FFT/DCT [Single]
 
 A-Form
 
@@ -138,7 +140,7 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Divide FFT/DCT [Double]
+# [DRAFT] Floating Divide FFT/DCT [Double]
 
 A-Form
 
@@ -157,17 +159,18 @@ Special Registers Altered:
     VXSNAN VXISI
     CR1          (if Rc=1)
 
-# Floating Multiply-Add FFT/DCT [Single]
+# [DRAFT] Floating Twin Multiply-Add DCT [Single]
 
-A-Form
+DCT-Form
 
-* ffmadds FRT,FRA,FRC,FRB (Rc=0)
-* ffmadds. FRT,FRA,FRC,FRB (Rc=1)
+* fdmadds FRT,FRA,FRB (Rc=0)
+* fdmadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, 1, 1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, -1, 1)
+    FRS <- FPADD32(FRT, FRB)
+    sub <- FPSUB32(FRT, FRB)
+    FRT <- FPMUL32(FRA, sub)
 
 Special Registers Altered:
 
@@ -176,17 +179,18 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Multiply-Sub FFT/DCT [Single]
+# [DRAFT] Floating Multiply-Add FFT [Single]
 
 A-Form
 
-* ffmsubs FRT,FRA,FRC,FRB (Rc=0)
-* ffmsubs. FRT,FRA,FRC,FRB (Rc=1)
+* ffmadds FRT,FRA,FRB (Rc=0)
+* ffmadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, 1, -1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, -1, -1)
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, 1, 1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, -1, 1)
 
 Special Registers Altered:
 
@@ -195,17 +199,18 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Negative Multiply-Add FFT/DCT [Single]
+# [DRAFT] Floating Multiply-Sub FFT [Single]
 
 A-Form
 
-* ffnmadds FRT,FRA,FRC,FRB (Rc=0)
-* ffnmadds. FRT,FRA,FRC,FRB (Rc=1)
+* ffmsubs FRT,FRA,FRB (Rc=0)
+* ffmsubs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1, -1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, 1, -1)
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, 1, -1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, -1, -1)
 
 Special Registers Altered:
 
@@ -214,17 +219,18 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
-# Floating Negative Multiply-Sub FFT/DCT [Single]
+# [DRAFT] Floating Negative Multiply-Add FFT [Single]
 
 A-Form
 
-* ffnmsubs FRT,FRA,FRC,FRB (Rc=0)
-* ffnmsubs. FRT,FRA,FRC,FRB (Rc=1)
+* ffnmadds FRT,FRA,FRB (Rc=0)
+* ffnmadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
-    FRT <- FPMULADD32(FRA, FRC, FRB, -1, 1)
-    FRS <- FPMULADD32(FRA, FRC, FRB, 1, 1)
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, -1, -1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, 1, -1)
 
 Special Registers Altered:
 
@@ -233,3 +239,22 @@ Special Registers Altered:
     VXSNAN VXISI VXIMZ
     CR1          (if Rc=1)
 
+# [DRAFT] Floating Negative Multiply-Sub FFT [Single]
+
+A-Form
+
+* ffnmsubs FRT,FRA,FRB (Rc=0)
+* ffnmsubs. FRT,FRA,FRB (Rc=1)
+
+Pseudo-code:
+
+    tmp <- FRT
+    FRT <- FPMULADD32(tmp, FRA, FRB, -1, 1)
+    FRS <- FPMULADD32(tmp, FRA, FRB, 1, 1)
+
+Special Registers Altered:
+
+    FPRF FR FI
+    FX OX UX XX
+    VXSNAN VXISI VXIMZ
+    CR1          (if Rc=1)