Refactor and fix LR/SC implementation (#217)

[riscv-isa-sim.git] / riscv / insns / lr_d.h

diff --git a/riscv/insns/lr_d.h b/riscv/insns/lr_d.h
index 5c8eff1090b379896bf995ba441ca67ac123f322..52090c31b87ccfbf1ef216e461a17d421059ee24 100644 (file)
--- a/riscv/insns/lr_d.h
+++ b/riscv/insns/lr_d.h
@@ -1,2 +1,4 @@
-require_xpr64;
-RD = mmu.load_reserved_int64(RS1);
+require_extension('A');
+require_rv64;
+MMU.acquire_load_reservation(RS1);
+WRITE_RD(MMU.load_int64(RS1));