Refactor and fix LR/SC implementation (#217)

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index c9bbac0e028da5a2965e0e7bf8243771b750a96c..b7080f0f0e4b464fa1d5825e91a3a3dd99919308 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -109,7 +109,7 @@ void sim_t::step(size_t n)
     if (current_step == INTERLEAVE)
     {
       current_step = 0;
-      procs[current_proc]->yield_load_reservation();
+      procs[current_proc]->get_mmu()->yield_load_reservation();
       if (++current_proc == procs.size()) {
         current_proc = 0;
         clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);