set dram_clk_freq to None

[ls2.git] / runsimsoc_hyperram.sh

diff --git a/runsimsoc_hyperram.sh b/runsimsoc_hyperram.sh
index 0fc1fe11fa4e4b6c91f2adfbe532b5a633bda088..78d3d56c0e0678816d406dd7a434e1a25ae13771 100755 (executable)
--- a/runsimsoc_hyperram.sh
+++ b/runsimsoc_hyperram.sh
@@ -10,7 +10,7 @@ QSPI_DIR=./qspi_model/Cy15b104qs/model/
 FIRMWARE=./coldboot/coldboot.bin
 
 # convert firmware to 32-bit hex
-python3 scripts/bin2hex.py ${FIRMWARE} 32 > ${QSPI_DIR}/firmware.hex
+python3 scripts/bin2hex.py ${FIRMWARE} 32 > firmware.hex
 
 # create the build_simsoc/top.il file with firmware baked-in
 python3 src/ls2.py isim ./coldboot/coldboot.bin
@@ -34,6 +34,7 @@ iverilog -Wall -g2012 -s simsoc_hyperram_tb -o simsoc \
        ${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v \
        ${LIB_DIR}/UDFDL5E_UDP_X.v \
        ${LIB_DIR}/OFS1P3DX.v \
+       ${LIB_DIR}/DELAYG.v \
        ${LIB_DIR}/IFS1P3DX.v \
     ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v \
     ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v \