merge litesata

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
index ec8de13413455e31c7c9b737bd656c564441b001..24013e2b03d5a64229fa31a6554c6c88a0c5f5ac 100644 (file)
--- a/setup.py
+++ b/setup.py
@@ -1,37 +1,37 @@
-#!/usr/bin/env python3
-
-import sys, os
-from setuptools import setup
-from setuptools import find_packages
-
-here = os.path.abspath(os.path.dirname(__file__))
-README = open(os.path.join(here, "README")).read()
-
-required_version = (3, 3)
-if sys.version_info < required_version:
-       raise SystemExit("LiteSATA requires python {0} or greater".format(
-               ".".join(map(str, required_version))))
-
-setup(
-       name="litesata",
-       version="unknown",
-       description="Generic open-source SATA1/2/3 controller",
-       long_description=README,
-       author="Florent Kermarrec",
-       author_email="florent@enjoy-digital.fr",
-       url="http://enjoy-digital.fr",
-       download_url="https://github.com/Florent-Kermarrec/litesata",
-       packages=find_packages(here),
-       license="GPL",
-       platforms=["Any"],
-       keywords="HDL ASIC FPGA hardware design",
-       classifiers=[
-               "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
-               "Environment :: Console",
-               "Development Status :: Alpha",
-               "Intended Audience :: Developers",
-               "License :: OSI Approved :: GNU General Public License (GPL)",
-               "Operating System :: OS Independent",
-               "Programming Language :: Python",
-       ],
-)
+#!/usr/bin/env python3\r
+\r
+import sys, os\r
+from setuptools import setup\r
+from setuptools import find_packages\r
+\r
+here = os.path.abspath(os.path.dirname(__file__))\r
+README = open(os.path.join(here, "README")).read()\r
+\r
+required_version = (3, 3)\r
+if sys.version_info < required_version:\r
+       raise SystemExit("MiSoC requires python {0} or greater".format(\r
+               ".".join(map(str, required_version))))\r
+\r
+setup(\r
+       name="misoclib",\r
+       version="unknown",\r
+       description="a high performance and small footprint SoC based on Migen",\r
+       long_description=README,\r
+       author="Sebastien Bourdeauducq",\r
+       author_email="sb@m-labs.hk",\r
+       url="http://m-labs.hk",\r
+       download_url="https://github.com/m-labs/misoc",\r
+       packages=find_packages(here),\r
+       license="BSD",\r
+       platforms=["Any"],\r
+       keywords="HDL ASIC FPGA hardware design",\r
+       classifiers=[\r
+               "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",\r
+               "Environment :: Console",\r
+               "Development Status :: Alpha",\r
+               "Intended Audience :: Developers",\r
+               "License :: OSI Approved :: BSD License",\r
+               "Operating System :: OS Independent",\r
+               "Programming Language :: Python",\r
+       ],\r
+)\r