Merge pull request #79 from xobs/fix-vexriscv-data-read

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
index 033a196cdfb8eb972c1fd8868ebca8dea22c61be..30a2e42f6804fe9e9b4451a12fd6ca0917ac0cc9 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -5,13 +5,13 @@ from setuptools import setup
 from setuptools import find_packages
 
 
-if sys.version_info[:3] < (3, 3):
-    raise SystemExit("You need Python 3.3+")
+if sys.version_info[:3] < (3, 5):
+    raise SystemExit("You need Python 3.5+")
 
 
 setup(
     name="litex",
-    version="0.1",
+    version="0.2.dev",
     description="Python tools to design FPGA cores and SoCs",
     long_description=open("README").read(),
     author="Florent Kermarrec",
@@ -25,19 +25,21 @@ setup(
     classifiers=[
         "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
         "Environment :: Console",
-        "Development Status :: Beta",
+        "Development Status :: Alpha",
         "Intended Audience :: Developers",
         "License :: OSI Approved :: BSD License",
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
     packages=find_packages(),
+    install_requires=["pyserial"],
     include_package_data=True,
     entry_points={
         "console_scripts": [
             "litex_term=litex.soc.tools.litex_term:main",
             "mkmscimg=litex.soc.tools.mkmscimg:main",
-            "litex_server=litex.soc.tools.remote.litex_server:main"
+            "litex_server=litex.soc.tools.remote.litex_server:main",
+            "vexriscv_bridge=litex.soc.tools.vexriscv_debug:main"
         ],
     },
 )