build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper...

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
index 39cbcf4640cb7b5a4e93ba92051a80a83343e6a7..55e4fe7195a5587037a9c72d9d9bcdb7f2426bfe 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -5,19 +5,20 @@ from setuptools import setup
 from setuptools import find_packages
 
 
-if sys.version_info[:3] < (3, 3):
-    raise SystemExit("You need Python 3.3+")
+if sys.version_info[:3] < (3, 5):
+    raise SystemExit("You need Python 3.5+")
 
 
 setup(
-    name="misoc",
-    version="1.0",
-    description="a high performance and small footprint SoC based on Migen",
+    name="litex",
+    version="0.2.dev",
+    description="Python tools to design FPGA cores and SoCs",
     long_description=open("README").read(),
-    author="Sebastien Bourdeauducq",
-    author_email="sb@m-labs.hk",
-    url="http://m-labs.hk",
-    download_url="https://github.com/m-labs/misoc",
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
+    download_url="https://github.com/enjoy-digital/litex",
+    test_suite="test",
     license="BSD",
     platforms=["Any"],
     keywords="HDL ASIC FPGA hardware design",
@@ -30,12 +31,16 @@ setup(
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
-    packages=find_packages(),
+    packages=find_packages(exclude=("test*", "sim*", "doc*")),
+    install_requires=["pyserial"],
     include_package_data=True,
     entry_points={
         "console_scripts": [
-            "flterm=misoc.tools.flterm:main",
-            "mkmscimg=misoc.tools.mkmscimg:main",
+            "mkmscimg=litex.soc.tools.mkmscimg:main",
+            "litex_term=litex.soc.tools.litex_term:main",
+            "litex_server=litex.soc.tools.remote.litex_server:main",
+            "litex_sim=litex.boards.targets.sim:main",
+            "litex_simple=litex.boards.targets.simple:main",
         ],
     },
 )