build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper...

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
index 8bc614c787bd9868e835ae9298998fcb74366125..55e4fe7195a5587037a9c72d9d9bcdb7f2426bfe 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -11,7 +11,7 @@ if sys.version_info[:3] < (3, 5):
 
 setup(
     name="litex",
-    version="0.1",
+    version="0.2.dev",
     description="Python tools to design FPGA cores and SoCs",
     long_description=open("README").read(),
     author="Florent Kermarrec",
@@ -31,14 +31,16 @@ setup(
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
-    packages=find_packages(),
+    packages=find_packages(exclude=("test*", "sim*", "doc*")),
     install_requires=["pyserial"],
     include_package_data=True,
     entry_points={
         "console_scripts": [
-            "litex_term=litex.soc.tools.litex_term:main",
             "mkmscimg=litex.soc.tools.mkmscimg:main",
-            "litex_server=litex.soc.tools.remote.litex_server:main"
+            "litex_term=litex.soc.tools.litex_term:main",
+            "litex_server=litex.soc.tools.remote.litex_server:main",
+            "litex_sim=litex.boards.targets.sim:main",
+            "litex_simple=litex.boards.targets.simple:main",
         ],
     },
 )