build/lattice/prjtrellis: modify generated verilog instead of creating a wrapper...

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
old mode 100644 (file)
new mode 100755 (executable)
index e73cf8c..55e4fe7
--- a/setup.py
+++ b/setup.py
@@ -5,21 +5,20 @@ from setuptools import setup
 from setuptools import find_packages
 
 
-required_version = (3, 3)
-if sys.version_info < required_version:
-    raise SystemExit("MiSoC requires python {0} or greater".format(
-        ".".join(map(str, required_version))))
+if sys.version_info[:3] < (3, 5):
+    raise SystemExit("You need Python 3.5+")
+
 
 setup(
-    name="misoc",
-    version="1.0",
-    description="a high performance and small footprint SoC based on Migen",
-    long_description=open("README.rst").read(),
-    author="Sebastien Bourdeauducq",
-    author_email="sb@m-labs.hk",
-    url="http://m-labs.hk",
-    download_url="https://github.com/m-labs/misoc",
-    packages=find_packages(),
+    name="litex",
+    version="0.2.dev",
+    description="Python tools to design FPGA cores and SoCs",
+    long_description=open("README").read(),
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
+    download_url="https://github.com/enjoy-digital/litex",
+    test_suite="test",
     license="BSD",
     platforms=["Any"],
     keywords="HDL ASIC FPGA hardware design",
@@ -32,4 +31,16 @@ setup(
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
+    packages=find_packages(exclude=("test*", "sim*", "doc*")),
+    install_requires=["pyserial"],
+    include_package_data=True,
+    entry_points={
+        "console_scripts": [
+            "mkmscimg=litex.soc.tools.mkmscimg:main",
+            "litex_term=litex.soc.tools.litex_term:main",
+            "litex_server=litex.soc.tools.remote.litex_server:main",
+            "litex_sim=litex.boards.targets.sim:main",
+            "litex_simple=litex.boards.targets.simple:main",
+        ],
+    },
 )