soc/cores/clock: different vco_freq_range for pll and mmcm
[litex.git] / setup.py
index 230a1e2e1d63ffbba26d6350e89cac0f7077533c..55e4fe7195a5587037a9c72d9d9bcdb7f2426bfe 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -5,13 +5,13 @@ from setuptools import setup
 from setuptools import find_packages
 
 
-if sys.version_info[:3] < (3, 3):
-    raise SystemExit("You need Python 3.3+")
+if sys.version_info[:3] < (3, 5):
+    raise SystemExit("You need Python 3.5+")
 
 
 setup(
     name="litex",
-    version="0.1",
+    version="0.2.dev",
     description="Python tools to design FPGA cores and SoCs",
     long_description=open("README").read(),
     author="Florent Kermarrec",
@@ -25,20 +25,22 @@ setup(
     classifiers=[
         "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
         "Environment :: Console",
-        "Development Status :: Beta",
+        "Development Status :: Alpha",
         "Intended Audience :: Developers",
         "License :: OSI Approved :: BSD License",
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
-    packages=find_packages(),
+    packages=find_packages(exclude=("test*", "sim*", "doc*")),
     install_requires=["pyserial"],
     include_package_data=True,
     entry_points={
         "console_scripts": [
-            "litex_term=litex.soc.tools.litex_term:main",
             "mkmscimg=litex.soc.tools.mkmscimg:main",
-            "litex_server=litex.soc.tools.remote.litex_server:main"
+            "litex_term=litex.soc.tools.litex_term:main",
+            "litex_server=litex.soc.tools.remote.litex_server:main",
+            "litex_sim=litex.boards.targets.sim:main",
+            "litex_simple=litex.boards.targets.simple:main",
         ],
     },
 )