csr: fix simple accessor alignment

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
index 033a196cdfb8eb972c1fd8868ebca8dea22c61be..59d07529373a517ea6a6123312fec9865cbc299f 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -1,43 +1,52 @@
 #!/usr/bin/env python3
 
-import sys
 from setuptools import setup
 from setuptools import find_packages
 
 
-if sys.version_info[:3] < (3, 3):
-    raise SystemExit("You need Python 3.3+")
-
-
 setup(
     name="litex",
-    version="0.1",
-    description="Python tools to design FPGA cores and SoCs",
-    long_description=open("README").read(),
+    description="Python SoC/Core builder for building FPGA based systems.",
     author="Florent Kermarrec",
     author_email="florent@enjoy-digital.fr",
     url="http://enjoy-digital.fr",
     download_url="https://github.com/enjoy-digital/litex",
     test_suite="test",
     license="BSD",
+    python_requires="~=3.6",
+    install_requires=[
+        "migen",
+        "pyserial",
+        "requests",
+        "pythondata-software-compiler_rt",
+    ],
+    packages=find_packages(exclude=("test*", "sim*", "doc*")),
+    include_package_data=True,
     platforms=["Any"],
     keywords="HDL ASIC FPGA hardware design",
     classifiers=[
         "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
         "Environment :: Console",
-        "Development Status :: Beta",
+        "Development Status :: Alpha",
         "Intended Audience :: Developers",
         "License :: OSI Approved :: BSD License",
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
-    packages=find_packages(),
-    include_package_data=True,
     entry_points={
         "console_scripts": [
-            "litex_term=litex.soc.tools.litex_term:main",
-            "mkmscimg=litex.soc.tools.mkmscimg:main",
-            "litex_server=litex.soc.tools.remote.litex_server:main"
+            # full names
+            "litex_term=litex.tools.litex_term:main",
+            "litex_server=litex.tools.litex_server:main",
+            "litex_jtag_uart=litex.tools.litex_jtag_uart:main",
+            "litex_crossover_uart=litex.tools.litex_crossover_uart:main",
+            "litex_sim=litex.tools.litex_sim:main",
+            "litex_read_verilog=litex.tools.litex_read_verilog:main",
+            "litex_simple=litex.boards.targets.simple:main",
+            # short names
+            "lxterm=litex.tools.litex_term:main",
+            "lxserver=litex.tools.litex_server:main",
+            "lxsim=litex.tools.litex_sim:main",
         ],
     },
 )