use brackets round (XLEN/2) in divw pseudocode

[openpower-isa.git] / setup.py

diff --git a/setup.py b/setup.py
index fbe317b040365d658474506bbd517c73b3b06dd1..5de8b0c4be0e5a8b9a3be2955d4636ee64d6cecd 100644 (file)
--- a/setup.py
+++ b/setup.py
@@ -61,7 +61,8 @@ setup(
             'pywriter=openpower.decoder.pseudo.pywriter:pywriter',
             'pyfnwriter=openpower.decoder.pseudo.pyfnwriter:pyfnwriter',
             'sv_analysis=openpower.sv.sv_analysis:process_csvs',
-            'pypowersim=openpower.decoder.isa.pypowersim:run_simulation'
+            'pypowersim=openpower.decoder.isa.pypowersim:run_simulation',
+            'pysvp64asm=openpower.sv.trans.svp64:asm_process'
         ]
     }
 )