name="litex",
version="0.2.dev",
description="Python tools to design FPGA cores and SoCs",
- long_description=open("README").read(),
+ long_description=open("README.md").read(),
author="Florent Kermarrec",
author_email="florent@enjoy-digital.fr",
url="http://enjoy-digital.fr",
"Programming Language :: Python",
],
packages=find_packages(exclude=("test*", "sim*", "doc*")),
- install_requires=["pyserial"],
+ install_requires=["migen", "pyserial"],
include_package_data=True,
entry_points={
"console_scripts": [
+ # full names
"litex_term=litex.tools.litex_term:main",
"litex_server=litex.tools.litex_server:main",
"litex_sim=litex.tools.litex_sim:main",
"litex_read_verilog=litex.tools.litex_read_verilog:main",
"litex_simple=litex.boards.targets.simple:main",
+ # short names
+ "lxterm=litex.tools.litex_term:main",
+ "lxserver=litex.tools.litex_server:main",
+ "lxsim=litex.tools.litex_sim:main",
],
},
)