soc/integration/csr_bridge: use registered version only when SDRAM is present.

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
index 46f8b6eebce3f1d6b9d454b651ab8e56a402d5e1..efefa52a4a085eed97c1b0812e2b5ae6a0be0228 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -14,17 +14,36 @@ setup(
     test_suite="test",
     license="BSD",
     python_requires="~=3.6",
-    install_requires=["migen", "pyserial"],
+    install_requires=[
+        "migen",
+        "pyserial",
+        "requests",
+        "pythondata-software-compiler_rt",
+    ],
     packages=find_packages(exclude=("test*", "sim*", "doc*")),
     include_package_data=True,
+    platforms=["Any"],
+    keywords="HDL ASIC FPGA hardware design",
+    classifiers=[
+        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+        "Environment :: Console",
+        "Development Status :: Alpha",
+        "Intended Audience :: Developers",
+        "License :: OSI Approved :: BSD License",
+        "Operating System :: OS Independent",
+        "Programming Language :: Python",
+    ],
     entry_points={
         "console_scripts": [
             # full names
             "litex_term=litex.tools.litex_term:main",
             "litex_server=litex.tools.litex_server:main",
+            "litex_jtag_uart=litex.tools.litex_jtag_uart:main",
+            "litex_crossover_uart=litex.tools.litex_crossover_uart:main",
             "litex_sim=litex.tools.litex_sim:main",
             "litex_read_verilog=litex.tools.litex_read_verilog:main",
             "litex_simple=litex.boards.targets.simple:main",
+            "litex_json2dts=litex.tools.litex_json2dts:main",
             # short names
             "lxterm=litex.tools.litex_term:main",
             "lxserver=litex.tools.litex_server:main",