litex: reorganize things, first work working version

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
old mode 100644 (file)
new mode 100755 (executable)
index 0f84b94..f1bb2ab
--- a/setup.py
+++ b/setup.py
@@ -1,37 +1,41 @@
 #!/usr/bin/env python3
 
-import sys, os
+import sys
 from setuptools import setup
 from setuptools import find_packages
 
-here = os.path.abspath(os.path.dirname(__file__))
-README = open(os.path.join(here, "README")).read()
 
-required_version = (3, 3)
-if sys.version_info < required_version:
-       raise SystemExit("LiteEth requires python {0} or greater".format(
-               ".".join(map(str, required_version))))
+if sys.version_info[:3] < (3, 3):
+    raise SystemExit("You need Python 3.3+")
+
 
 setup(
-       name="liteeth",
-       version="unknown",
-       description="small footprint and configurable Ethernet core",
-       long_description=README,
-       author="Florent Kermarrec",
-       author_email="florent@enjoy-digital.fr",
-       url="http://enjoy-digital.fr",
-       download_url="https://github.com/enjoy-digital/liteeth",
-       packages=find_packages(here),
-       license="GPL",
-       platforms=["Any"],
-       keywords="HDL ASIC FPGA hardware design",
-       classifiers=[
-               "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
-               "Environment :: Console",
-               "Development Status :: Alpha",
-               "Intended Audience :: Developers",
-               "License :: OSI Approved :: GNU General Public License (GPL)",
-               "Operating System :: OS Independent",
-               "Programming Language :: Python",
-       ],
+    name="litex",
+    version="1.0",
+    description="Python tools to design FPGA cores and SoCs",
+    long_description=open("README").read(),
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
+    download_url="https://github.com/enjoy-digital/litex",
+    license="BSD",
+    platforms=["Any"],
+    keywords="HDL ASIC FPGA hardware design",
+    classifiers=[
+        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+        "Environment :: Console",
+        "Development Status :: Beta",
+        "Intended Audience :: Developers",
+        "License :: OSI Approved :: BSD License",
+        "Operating System :: OS Independent",
+        "Programming Language :: Python",
+    ],
+    packages=find_packages(),
+    include_package_data=True,
+    entry_points={
+        "console_scripts": [
+            "flterm=litex.soc.tools.flterm:main",
+            "mkmscimg=litex.soc.tools.mkmscimg:main",
+        ],
+    },
 )