soc/interconnect/stream: reintroduce PipelinedActor/Buffer

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
old mode 100644 (file)
new mode 100755 (executable)
index 41af6c8..f1bb2ab
--- a/setup.py
+++ b/setup.py
@@ -1,38 +1,41 @@
-#!/usr/bin/env python3\r
-\r
-import sys\r
-import os\r
-from setuptools import setup\r
-from setuptools import find_packages\r
-\r
-here = os.path.abspath(os.path.dirname(__file__))\r
-README = open(os.path.join(here, "README")).read()\r
-\r
-required_version = (3, 3)\r
-if sys.version_info < required_version:\r
-    raise SystemExit("MiSoC requires python {0} or greater".format(\r
-        ".".join(map(str, required_version))))\r
-\r
-setup(\r
-    name="misoclib",\r
-    version="unknown",\r
-    description="a high performance and small footprint SoC based on Migen",\r
-    long_description=README,\r
-    author="Sebastien Bourdeauducq",\r
-    author_email="sb@m-labs.hk",\r
-    url="http://m-labs.hk",\r
-    download_url="https://github.com/m-labs/misoc",\r
-    packages=find_packages(here),\r
-    license="BSD",\r
-    platforms=["Any"],\r
-    keywords="HDL ASIC FPGA hardware design",\r
-    classifiers=[\r
-        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",\r
-        "Environment :: Console",\r
-        "Development Status :: Alpha",\r
-        "Intended Audience :: Developers",\r
-        "License :: OSI Approved :: BSD License",\r
-        "Operating System :: OS Independent",\r
-        "Programming Language :: Python",\r
-    ],\r
-)\r
+#!/usr/bin/env python3
+
+import sys
+from setuptools import setup
+from setuptools import find_packages
+
+
+if sys.version_info[:3] < (3, 3):
+    raise SystemExit("You need Python 3.3+")
+
+
+setup(
+    name="litex",
+    version="1.0",
+    description="Python tools to design FPGA cores and SoCs",
+    long_description=open("README").read(),
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
+    download_url="https://github.com/enjoy-digital/litex",
+    license="BSD",
+    platforms=["Any"],
+    keywords="HDL ASIC FPGA hardware design",
+    classifiers=[
+        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+        "Environment :: Console",
+        "Development Status :: Beta",
+        "Intended Audience :: Developers",
+        "License :: OSI Approved :: BSD License",
+        "Operating System :: OS Independent",
+        "Programming Language :: Python",
+    ],
+    packages=find_packages(),
+    include_package_data=True,
+    entry_points={
+        "console_scripts": [
+            "flterm=litex.soc.tools.flterm:main",
+            "mkmscimg=litex.soc.tools.mkmscimg:main",
+        ],
+    },
+)