soc/interconnect/stream: reintroduce PipelinedActor/Buffer

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
old mode 100644 (file)
new mode 100755 (executable)
index ba67556..f1bb2ab
--- a/setup.py
+++ b/setup.py
@@ -10,25 +10,32 @@ if sys.version_info[:3] < (3, 3):
 
 
 setup(
-    name="misoc",
+    name="litex",
     version="1.0",
-    description="a high performance and small footprint SoC based on Migen",
-    long_description=open("README.rst").read(),
-    author="Sebastien Bourdeauducq",
-    author_email="sb@m-labs.hk",
-    url="http://m-labs.hk",
-    download_url="https://github.com/m-labs/misoc",
-    packages=find_packages(),
+    description="Python tools to design FPGA cores and SoCs",
+    long_description=open("README").read(),
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
+    download_url="https://github.com/enjoy-digital/litex",
     license="BSD",
     platforms=["Any"],
     keywords="HDL ASIC FPGA hardware design",
     classifiers=[
         "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
         "Environment :: Console",
-        "Development Status :: Alpha",
+        "Development Status :: Beta",
         "Intended Audience :: Developers",
         "License :: OSI Approved :: BSD License",
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
+    packages=find_packages(),
+    include_package_data=True,
+    entry_points={
+        "console_scripts": [
+            "flterm=litex.soc.tools.flterm:main",
+            "mkmscimg=litex.soc.tools.mkmscimg:main",
+        ],
+    },
 )