import AXI4_Types::*;
import Semi_FIFOF::*;
import AXI4Lite_AXI4_Bridge::*;
+ import slow_memory_map::*;
`include "instance_defines.bsv"
- /* ==== define the AXI Addresses ==== */
-{2}
- /*====== AXI4 Lite slave declarations =======*/
-
-{3}
+ /* ==== define the number of slow peripheral irqs ==== */
+{11}
/*===========================*/
/*=== package imports ===*/
import Clocks::*;
+ import ifc_sync:: *;
import GetPut::*;
import ClientServer::*;
import Connectable::*;
`ifdef AXIEXP
import axiexpansion ::*;
`endif
- `ifdef QSPI
- import qspi :: *;
- `endif
/*=====================================*/
/*===== interface declaration =====*/
`endif
endinterface
interface Ifc_slow_peripherals;
- interface AXI4_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+ interface AXI4_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
interface SP_dedicated_ios slow_ios;
`ifdef CLINT
method Bit#(1) msip_int;
method Bit#(1) mtip_int;
method Bit#(`DATA) mtime;
`endif
- `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note; `endif
- interface IOCellSide iocell_side; // mandatory interface
+ `ifdef PLIC method ActionValue#(Tuple2#(Bool,Bool)) intrpt_note;
+ `endif
+ interface IOCellSide iocell_side; // mandatory interface
+ `ifdef PLIC
{1}
+ `endif
endinterface
/*================================*/
- function Tuple2#(Bool, Bit#(TLog#(Num_Slow_Slaves)))
- fn_address_mapping (Bit#(`ADDR) addr);
- `ifdef CLINT
- if(addr>=`ClintBase && addr<=`ClintEnd)
- return tuple2(True,fromInteger(valueOf(CLINT_slave_num)));
- else
- `endif
- `ifdef PLIC
- if(addr>=`PLICBase && addr<=`PLICEnd)
- return tuple2(True,fromInteger(valueOf(Plic_slave_num)));
- else
- `endif
- `ifdef AXIEXP
- if(addr>=`AxiExp1Base && addr<=`AxiExp1End)
- return tuple2(True,fromInteger(valueOf(AxiExp1_slave_num)));
- else
- `endif
-{4}
- return tuple2(False,?);
- endfunction
-
(*synthesize*)
module mkslow_peripherals#(Clock fast_clock, Reset fast_reset,
Clock uart_clock, Reset uart_reset
/*======= Module declarations for each peripheral =======*/
{5}
`ifdef CLINT
- Ifc_clint clint <- mkclint();
+ Ifc_clint clint <- mkclint();
`endif
`ifdef PLIC
- Ifc_PLIC_AXI plic <- mkplicperipheral();
- Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
- Vector#(32, FIFO#(bit)) ff_gateway_queue <- replicateM(mkFIFO);
+ Ifc_PLIC_AXI plic <- mkplicperipheral();
+ Wire#(Bit#(TLog#(`INTERRUPT_PINS))) interrupt_id <- mkWire();
+ Vector#(`INTERRUPT_PINS, FIFO#(bit))
+ ff_gateway_queue <- replicateM(mkFIFO);
`endif
`ifdef AXIEXP
- Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
+ Ifc_AxiExpansion axiexp1 <- mkAxiExpansion();
`endif
- Ifc_pinmux pinmux <- mkpinmux; // mandatory
+ Ifc_pinmux pinmux <- mkpinmux; // mandatory
+{14}
+
/*=======================================================*/
- AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `ADDR, `DATA,`USERSPACE)
- slow_fabric <- mkAXI4_Lite_Fabric(fn_address_mapping);
+ AXI4_Lite_Fabric_IFC #(1, Num_Slow_Slaves, `PADDR, `DATA,`USERSPACE)
+ slow_fabric <- mkAXI4_Lite_Fabric(fn_slow_address_mapping);
Ifc_AXI4Lite_AXI4_Bridge
- bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
+ bridge<-mkAXI4Lite_AXI4_Bridge(fast_clock,fast_reset);
- mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
+ mkConnection (bridge.axi4_lite_master, slow_fabric.v_from_masters [0]);
/*======= Slave connections to AXI4Lite fabric =========*/
{6}
`ifdef CLINT
/*========== pinmux connections ============*/
{7}
{8}
+
+ /*=================== PLIC Connections ==================== */
+`ifdef PLIC
+{10}
+
rule rl_completion_msg_from_plic;
- let id <- plic.intrpt_completion;
+ let id <- plic.intrpt_completion;
interrupt_id <= id;
- `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
- endrule
+ `ifdef verbose
+ $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id);
+ `endif
+ endrule
- for(Integer i=0; i <32; i=i+1) begin
+ for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
rule deq_gateway_queue;
if(interrupt_id==fromInteger(i)) begin
ff_gateway_queue[i].deq;
- `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
+ `ifdef verbose
+ $display($time,"Dequeing the Interrupt request for ID: %d",i);
+ `endif
end
endrule
end
- /* for connectin inputs from pinmux as itnerrupts
- rule connect_pinmux_eint;
- wr_interrupt<= pinmux.peripheral_side.eint_input;
+ /*TODO DMA interrupt need to be connected to the plic */
+ for(Integer i=1; i<8; i=i+1) begin
+ rule rl_connect_dma_interrupts_to_plic;
+ `ifdef DMA
+ if(dma.interrupt_to_processor[i-1]==1'b1) begin
+ ff_gateway_queue[i].enq(1);
+ plic.ifc_external_irq[i].irq_frm_gateway(True);
+ end
+ `else
+ ff_gateway_queue[i].enq(0);
+ `endif
endrule
- */
- // NEEL EDIT OVER
- /*=======================================================*/
- /*=================== PLIC Connections ==================== */
- `ifdef PLIC_main
- /*TODO DMA interrupt need to be connected to the plic
- for(Integer i=1; i<8; i=i+1) begin
- `ifdef DMA
- rule rl_connect_dma_interrupts_to_plic;
- if(dma.interrupt_to_processor[i-1]==1'b1) begin
- ff_gateway_queue[i].enq(1);
- plic.ifc_external_irq[i].irq_frm_gateway(True);
- end
- endrule
- `else
- rule rl_connect_dma_interrupts_to_plic;
- ff_gateway_queue[i].enq(0);
- endrule
- `endif
- end
- */
- rule rl_connect_i2c0_to_plic;
- `ifdef I2C0
- if(i2c0.isint()==1'b1) begin
- ff_gateway_queue[8].enq(1);
- plic.ifc_external_irq[8].irq_frm_gateway(True);
- end
- `else
- ff_gateway_queue[8].enq(0);
- `endif
- endrule
-
- rule rl_connect_i2c1_to_plic;
- `ifdef I2C1
- if(i2c1.isint()==1'b1) begin
- ff_gateway_queue[9].enq(1);
- plic.ifc_external_irq[9].irq_frm_gateway(True);
- end
- `else
- ff_gateway_queue[9].enq(0);
- `endif
- endrule
-
- rule rl_connect_i2c0_timerint_to_plic;
- `ifdef I2C0
- if(i2c0.timerint()==1'b1) begin
- ff_gateway_queue[10].enq(1);
- plic.ifc_external_irq[10].irq_frm_gateway(True);
- end
- `else
- ff_gateway_queue[10].enq(0);
- `endif
- endrule
-
- rule rl_connect_i2c1_timerint_to_plic;
- `ifdef I2C1
- if(i2c1.timerint()==1'b1) begin
- ff_gateway_queue[11].enq(1);
- plic.ifc_external_irq[11].irq_frm_gateway(True);
- end
- `else
- ff_gateway_queue[11].enq(0);
- `endif
- endrule
-
- rule rl_connect_i2c0_isber_to_plic;
- `ifdef I2C0
- if(i2c0.isber()==1'b1) begin
- ff_gateway_queue[12].enq(1);
- plic.ifc_external_irq[12].irq_frm_gateway(True);
- end
- `else
- ff_gateway_queue[12].enq(0);
- `endif
- endrule
-
- rule rl_connect_i2c1_isber_to_plic;
- `ifdef I2C1
- if(i2c1.isber()==1'b1) begin
- ff_gateway_queue[13].enq(1);
- plic.ifc_external_irq[13].irq_frm_gateway(True);
- end
- `else
- ff_gateway_queue[13].enq(0);
- `endif
- endrule
-
- for(Integer i = 14; i < 20; i=i+1) begin
- rule rl_connect_qspi0_to_plic;
- `ifdef QSPI0
- if(qspi0.interrupts()[i-14]==1'b1) begin
- ff_gateway_queue[i].enq(1);
- plic.ifc_external_irq[i].irq_frm_gateway(True);
- end
- `else
- ff_gateway_queue[i].enq(0);
- `endif
- endrule
- end
-
- for(Integer i = 20; i<26; i=i+1) begin
- rule rl_connect_qspi1_to_plic;
- `ifdef QSPI1
- if(qspi1.interrupts()[i-20]==1'b1) begin
- ff_gateway_queue[i].enq(1);
- plic.ifc_external_irq[i].irq_frm_gateway(True);
- end
- `else
- ff_gateway_queue[i].enq(0);
- `endif
- endrule
- end
-
- `ifdef UART0
- SyncBitIfc#(Bit#(1)) uart0_interrupt <-
- mkSyncBitToCC(sp_clock, uart_reset);
- rule synchronize_the_uart0_interrupt;
- uart0_interrupt.send(uart0.irq);
- endrule
- `endif
- rule rl_connect_uart_to_plic;
- `ifdef UART0
- if(uart0_interrupt.read==1'b1) begin
- ff_gateway_queue[27].enq(1);
- plic.ifc_external_irq[27].irq_frm_gateway(True);
- end
-
- `else
- ff_gateway_queue[27].enq(0);
- `endif
- endrule
-
- for(Integer i = 28; i<`INTERRUPT_PINS; i=i+1) begin
- rule rl_raise_interrupts;
- if((i-28)<`IONum) begin //Peripheral interrupts
- if(gpio.to_plic[i-28]==1'b1) begin
- plic.ifc_external_irq[i].irq_frm_gateway(True);
- ff_gateway_queue[i].enq(1);
- end
- end
- endrule
- end
-
- rule rl_completion_msg_from_plic;
- let id <- plic.intrpt_completion;
- interrupt_id <= id;
- `ifdef verbose $display("Dequeing the FIFO -- PLIC Interrupt Serviced id: %d",id); `endif
- endrule
-
- for(Integer i=0; i <`INTERRUPT_PINS; i=i+1) begin
- rule deq_gateway_queue;
- if(interrupt_id==fromInteger(i)) begin
- ff_gateway_queue[i].deq;
- `ifdef $display($time,"Dequeing the Interrupt request for ID: %d",i); `endif
- end
- endrule
- end
-
+ end
- `endif
- /*======================================================= */
+`endif // end PLIC
+ /*======================================================= */
/* ===== interface definition =======*/
interface axi_slave=bridge.axi_slave;
method mtip_int=clint.mtip_int;
method mtime=clint.mtime;
`endif
- `ifdef I2C0
- method i2c0_isint=i2c0.isint;
- `endif
- `ifdef I2C1
- method i2c1_isint=i2c1.isint;
- `endif
- `ifdef QSPI0 method qspi0_isint=qspi0.interrupts[5]; `endif
- `ifdef QSPI1 method qspi1_isint=qspi1.interrupts[5]; `endif
- `ifdef UART0 method uart0_intr=uart0.irq; `endif
+`ifdef PLIC
+{12}
+`endif // end PLIC
interface SP_dedicated_ios slow_ios;
-/* template for dedicated peripherals
+ /* template for dedicated peripherals
`ifdef UART0
interface uart0_coe=uart0.coe_rs232;
`endif
interface axiexp1_out=axiexp1.slave_out;
interface axiexp1_in=axiexp1.slave_in;
`endif
- `ifdef PWM_AXI4Lite
- interface pwm_o = pwm_bus.pwm_io;
- `endif
-*/
+ `ifdef PWM_AXI4Lite
+ interface pwm_o = pwm_bus.pwm_io;
+ `endif
+ */
endinterface
- // NEEL EDIT
- interface iocell_side=pinmux.iocell_side;
- interface pad_config0= gpioa.pad_config;
- // NEEL EDIT OVER
+ interface iocell_side=pinmux.iocell_side;
+{9}
+{13}
/*===================================*/
endmodule
endpackage
projects / pinmux.git / blobdiff