SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------
*/
-package Soc;
+package socgen;
/*====== Package imports === */
import FIFO::*;
import FIFOF::*;
import Vector::*;
import Connectable::*;
import Clocks::*;
- /*========================== */
+
/*=== Project imports === */
import ConcatReg::*;
import AXI4_Types::*;
import defined_types::*;
import MemoryMap :: *;
import slow_peripherals::*;
+ import fast_memory_map::*;
+ import slow_memory_map::*;
`ifdef DEBUG
`include "defines.bsv"
`endif
`include "instance_defines.bsv"
+ `include "core_parameters.bsv"
{8}
- /*====== AXI4 slave declarations =======*/
-{3}
- /*====== AXI4 Master declarations =======*/
-{4}
-
`ifdef DMA
import DMA :: *;
/*========================= */
interface Ifc_Soc;
- interface SP_ios slow_ios;
+ interface SP_dedicated_ios slow_ios;
(*always_ready,always_enabled*)
method Action boot_sequence(Bit#(1) bootseq);
`ifdef SDRAM
(*always_ready*) interface Ifc_sdram_out sdram_out;
`endif
- ifdef DDR
+ `ifdef DDR
(*prefix="M_AXI"*) interface
- AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
+ AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
`endif
`ifdef HYPER
(*always_ready,always_enabled*)
{1}
endinterface
+ //============ mkSoc module =================
+
(*synthesize*)
module mkSoc #(Bit#(`VADDR) reset_vector,
Clock slow_clock, Reset slow_reset, Clock uart_clock,
Ifc_vme_top vme <-mkvme_top();
`endif
Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
- core_clock, core_reset, uart_clock,
- uart_reset, clocked_by slow_clock ,
- reset_by slow_reset
+ core_clock, core_reset,
+ uart_clock, uart_reset,
+ clocked_by slow_clock, reset_by slow_reset
`ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
+ // clock sync mkConnections
+{12}
+
// Fabric
- AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
- `PADDR, `Reg_width,`USERSPACE)
+ AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
+ `PADDR, `DATA,`USERSPACE)
fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
// Connect traffic generators to fabric
mkSyncBitToCC(slow_clock,slow_reset);
SyncBitIfc#(Bit#(1)) clint_msip_int <-
mkSyncBitToCC(slow_clock,slow_reset);
- Reg#(Bit#(`Reg_width)) clint_mtime_value <-
+ Reg#(Bit#(`DATA)) clint_mtime_value <-
mkSyncRegToCC(0,slow_clock,slow_reset);
rule synchronize_clint_data;
clint_mtip_int.send(slow_peripherals.mtip_int);