import Clocks::*;
/*=== Project imports === */
+ import ifc_sync:: *;
import ConcatReg::*;
import AXI4_Types::*;
import AXI4_Fabric::*;
import defined_types::*;
import MemoryMap :: *;
import slow_peripherals::*;
+ import fast_memory_map::*;
+ import slow_memory_map::*;
`ifdef DEBUG
`include "defines.bsv"
`endif
/*========================= */
interface Ifc_Soc;
- interface SP_ios slow_ios;
+ interface SP_dedicated_ios slow_ios;
+ interface IOCellSide iocell_side;
(*always_ready,always_enabled*)
method Action boot_sequence(Bit#(1) bootseq);
`endif
`ifdef DDR
(*prefix="M_AXI"*) interface
- AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+ AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
`endif
`ifdef HYPER
(*always_ready,always_enabled*)
Ifc_vme_top vme <-mkvme_top();
`endif
Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
- core_clock, core_reset, uart_clock,
- uart_reset, clocked_by slow_clock ,
- reset_by slow_reset
+ core_clock, core_reset,
+ uart_clock, uart_reset,
+ clocked_by slow_clock, reset_by slow_reset
`ifdef PWM_AXI4Lite , ext_pwm_clock `endif );
+ // clock sync mkConnections
+{12}
+
// Fabric
- AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
- `ADDR, `DATA,`USERSPACE)
+ AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
+ `PADDR, `DATA,`USERSPACE)
fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
// Connect traffic generators to fabric
interface master=fabric.v_to_slaves
[fromInteger(valueOf(Sdram_slave_num))];
`endif
- interface slow_ios=slow_peripherals.slow_ios;
+ interface slow_ios = slow_peripherals.slow_ios;
+ interface iocell_side = slow_peripherals.iocell_side;
+
{6}
endmodule
endpackage