AddingPeripherals.mdwn

[pinmux.git] / src / bsv / bsv_lib / soc_template.bsv

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index 9c27b1d03e3a1680cc3628aff75b371f5ff0f508..3d33f8edc95581c0d153e888dada5654eff8deb4 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -40,12 +40,15 @@ package socgen;
     import Clocks::*;
 
     /*=== Project imports === */
+    import ifc_sync:: *;
     import ConcatReg::*;
     import AXI4_Types::*;
     import AXI4_Fabric::*;
     import defined_types::*;
     import MemoryMap            :: *;
     import slow_peripherals::*;
+    import fast_memory_map::*;
+    import slow_memory_map::*;
 `ifdef DEBUG
     `include "defines.bsv"
 `endif
@@ -59,9 +62,6 @@ package socgen;
     `ifdef BOOTROM
         import BootRom                 ::*;
     `endif
-    `ifdef SDRAM
-        import sdr_top                  :: *;
-    `endif
     `ifdef BRAM
         import Memory_AXI4     ::*;
     `endif
@@ -80,14 +80,12 @@ package socgen;
     `ifdef VME
         import vme_master::*;
     `endif
-    `ifdef FlexBus
-        import FlexBus_Types::*;
-    `endif
 {0}
 
     /*========================= */
     interface Ifc_Soc;
-        interface SP_ios slow_ios;
+        interface SP_dedicated_ios slow_ios;
+        interface IOCellSide iocell_side;
         (*always_ready,always_enabled*)
         method Action boot_sequence(Bit#(1) bootseq);
             
@@ -96,7 +94,7 @@ package socgen;
         `endif
         `ifdef DDR
             (*prefix="M_AXI"*) interface
-                   AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+                   AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
         `endif
         `ifdef HYPER
              (*always_ready,always_enabled*)   
@@ -128,9 +126,6 @@ package socgen;
         `ifdef BOOTROM
             BootRom_IFC bootrom <-mkBootRom;
         `endif
-        `ifdef SDRAM
-            Ifc_sdr_slave sdram<- mksdr_axi4_slave(clk0);
-        `endif
         `ifdef BRAM
             Memory_IFC#(`SDRAMMemBase,`Addr_space)main_memory <- 
                         mkMemory("code.mem.MSB","code.mem.LSB","MainMEM");
@@ -145,14 +140,17 @@ package socgen;
             Ifc_vme_top             vme             <-mkvme_top();
             `endif     
         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
-                          core_clock, core_reset, uart_clock, 
-                          uart_reset, clocked_by slow_clock ,
-                          reset_by slow_reset 
+                          core_clock, core_reset,
+                          uart_clock, uart_reset,
+                          clocked_by slow_clock, reset_by slow_reset
                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );        
 
+        // clock sync mkConnections
+{12}
+
         // Fabric
-        AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
-                          `ADDR, `DATA,`USERSPACE)
+        AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
+                          `PADDR, `DATA,`USERSPACE)
                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 
         // Connect traffic generators to fabric
@@ -168,6 +166,7 @@ package socgen;
          mkConnection (dma.mmu, fabric.v_from_masters
                               [fromInteger(valueOf(DMA_master_num))]);
         `endif
+{13}
 
 
         // Connect fabric to memory slaves
@@ -307,7 +306,9 @@ package socgen;
           interface master=fabric.v_to_slaves
                                 [fromInteger(valueOf(Sdram_slave_num))];
         `endif
-        interface slow_ios=slow_peripherals.slow_ios;
+        interface slow_ios = slow_peripherals.slow_ios;
+        interface iocell_side = slow_peripherals.iocell_side;
+
 {6}
     endmodule
 endpackage