fix includes

[pinmux.git] / src / bsv / bsv_lib / soc_template.bsv

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index 9d853f7f93c4a13b9a7ba6be806541939cfcf34b..c722604ff12f5073ba737b5511f408659d578ad2 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -28,7 +28,7 @@ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 -------------------------------------------------------------------
 */
-package Soc;
+package socgen;
     /*====== Package imports === */
     import FIFO::*;
     import FIFOF::*;
@@ -38,7 +38,7 @@ package Soc;
     import Vector::*;
     import Connectable::*;
     import Clocks::*;
-    /*========================== */
+
     /*=== Project imports === */
     import ConcatReg::*;
     import AXI4_Types::*;
@@ -46,14 +46,14 @@ package Soc;
     import defined_types::*;
     import MemoryMap            :: *;
     import slow_peripherals::*;
+    import fast_memory_map::*;
+    import slow_memory_map::*;
+`ifdef DEBUG
     `include "defines.bsv"
+`endif
     `include "instance_defines.bsv"
+    `include "core_parameters.bsv"
 {8}
-    /*====== AXI4 slave declarations =======*/
-{3}
-    /*====== AXI4 Master declarations =======*/
-{4}
-
 
     `ifdef DMA
         import DMA                              :: *;
@@ -89,16 +89,16 @@ package Soc;
 
     /*========================= */
     interface Ifc_Soc;
-        interface SP_ios slow_ios;
+        interface SP_dedicated_ios slow_ios;
         (*always_ready,always_enabled*)
         method Action boot_sequence(Bit#(1) bootseq);
             
         `ifdef SDRAM 
             (*always_ready*) interface Ifc_sdram_out sdram_out; 
         `endif
-        ifdef DDR
+        `ifdef DDR
             (*prefix="M_AXI"*) interface
-                   AXI4_Master_IFC#(`PADDR, `Reg_width, `USERSPACE) master;
+                   AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
         `endif
         `ifdef HYPER
              (*always_ready,always_enabled*)   
@@ -109,12 +109,11 @@ package Soc;
              interface Vme_out  proc_ifc;
              interface Data_bus_inf proc_dbus;
         `endif
-        `ifdef FlexBus
-             interface FlexBus_Master_IFC flexbus_out;
-        `endif
 {1}
     endinterface
 
+    //============ mkSoc module =================
+
     (*synthesize*)
     module mkSoc #(Bit#(`VADDR) reset_vector,
                  Clock slow_clock, Reset slow_reset, Clock uart_clock, 
@@ -147,10 +146,6 @@ package Soc;
             `ifdef VME
             Ifc_vme_top             vme             <-mkvme_top();
             `endif     
-        `ifdef FlexBus
-            AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(32, 64,0)
-                            flexbus <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
-        `endif
         Ifc_slow_peripherals slow_peripherals <-mkslow_peripherals(
                           core_clock, core_reset, uart_clock, 
                           uart_reset, clocked_by slow_clock ,
@@ -158,8 +153,8 @@ package Soc;
                           `ifdef PWM_AXI4Lite , ext_pwm_clock `endif );        
 
         // Fabric
-        AXI4_Fabric_IFC #(Num_Masters, Num_Slaves,
-                          `PADDR, `Reg_width,`USERSPACE)
+        AXI4_Fabric_IFC #(Num_Masters, Num_Fast_Slaves,
+                          `PADDR, `DATA,`USERSPACE)
                         fabric <- mkAXI4_Fabric(fn_addr_to_slave_num);
 
         // Connect traffic generators to fabric
@@ -219,11 +214,9 @@ package Soc;
                               [fromInteger(valueOf(VME_slave_num))],
                               vme.slave_axi_vme);
             `endif
-            `ifdef FlexBus
-                mkConnection (fabric.v_to_slaves
-                              [fromInteger(valueOf(FlexBus_slave_num))],
-                              flexbus.axi_side);
-            `endif
+
+//          pin connections
+{9}
 
             // fabric connections
 {5}
@@ -277,7 +270,7 @@ package Soc;
                                         mkSyncBitToCC(slow_clock,slow_reset);
             SyncBitIfc#(Bit#(1)) clint_msip_int <-
                                         mkSyncBitToCC(slow_clock,slow_reset);
-            Reg#(Bit#(`Reg_width)) clint_mtime_value <-
+            Reg#(Bit#(`DATA)) clint_mtime_value <-
                                         mkSyncRegToCC(0,slow_clock,slow_reset);
             rule synchronize_clint_data;
                 clint_mtip_int.send(slow_peripherals.mtip_int);
@@ -306,9 +299,6 @@ package Soc;
         `ifdef VME
             interface  proc_ifc = vme.proc_ifc;
             interface   proc_dbus = vme.proc_dbus;
-        `endif 
-        `ifdef FlexBus
-            interface flexbus_out = flexbus.flexbus_side;
         `endif 
          method Action boot_sequence(Bit#(1) bootseq) = 
                             core.boot_sequence(bootseq);