generate instance defines, fix lots of random typos

[pinmux.git] / src / bsv / bus_transactors.py

diff --git a/src/bsv/bus_transactors.py b/src/bsv/bus_transactors.py
index b4ebefd5d4d37ed7b9b842382f16c5e9e8841792..fc3e81e0b998f67bbe2fd1011ed3315343075dc3 100644 (file)
--- a/src/bsv/bus_transactors.py
+++ b/src/bsv/bus_transactors.py
@@ -1,7 +1,7 @@
 
 axi4_lite = '''
 // this file is auto-generated, please do not edit
-package gpio_instance;
+package bus;
     /*==== Package imports ==== */
     import TriState          ::*;
     import Vector                ::*;
@@ -17,24 +17,18 @@ package gpio_instance;
     /*============================ */
 
   // instantiation template
-    interface GPIO_real;
-    interface PeripheralSide peripheral_side;
-    interface GPIO_config#(32) bankA_config;
-        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) bankA_slave;
-    interface GPIO_config#(15) bankB_config;
-        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) bankB_slave;
-
-    interface MUX_config#(32) muxbankA_config;
-        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxbankA_slave;
-    interface MUX_config#(15) muxbankB_config;
-        interface AXI4_Lite_Slave_IFC#({0},{1},{2}) muxbankB_slave;
+    interface BUS;
+        interface PeripheralSide peripheral_side;
+        interface IOCellSide iocell_side;
+{1}
     endinterface
   (*synthesize*)
-  module mkgpio_real(GPIO_real);
+  module mkbus(BUS);
     Ifc_pinmux pinmux <-mkpinmux;
     // gpio/mux declarations
-{3}
+{0}
     interface peripheral_side=pinmux.peripheral_side;
+    interface iocell_side=pinmux.iocell_side;
   endmodule
 endpackage
 '''