from bsv.wire_def import generic_io # special case
from bsv.wire_def import muxwire # special case
-
+from ifacebase import InterfacesBase
class Pin(object):
""" pin interface declaration.
enabled=True,
io=False,
action=False,
- bitspec=None):
+ bitspec=None,
+ outenmode=False):
self.name = name
self.ready = ready
self.enabled = enabled
self.io = io
self.action = action
self.bitspec = bitspec if bitspec else 'Bit#(1)'
+ self.outenmode = outenmode
+
+ # bsv will look like this (method declaration):
+ """
+ (*always_ready,always_enabled*) method Bit#(1) io0_cell_outen;
+ (*always_ready,always_enabled,result="io"*) method
+ Action io0_inputval (Bit#(1) in);
+ """
- def ifacefmt(self, fmtfn=None):
+ def ifacefmt(self, fmtfn):
res = ' '
status = []
if self.ready:
res += ";"
return res
- def ifacedef(self, fmtoutfn=None, fmtinfn=None, fmtdecfn=None):
+ # sample bsv method definition :
+ """
+ method Action cell0_mux(Bit#(2) in);
+ wrcell0_mux<=in;
+ endmethod
+ """
+
+ def ifacedef(self, fmtoutfn, fmtinfn, fmtdecfn):
res = ' method '
if self.action:
fmtname = fmtinfn(self.name)
fmtname = fmtoutfn(self.name)
res += "%s=%s;" % (self.name, fmtname)
return res
+ # sample bsv wire (wire definiton):
+ """
+ Wire#(Bit#(2)) wrcell0_mux<-mkDWire(0);
+ """
- def wirefmt(self, fmtoutfn=None, fmtinfn=None, fmtdecfn=None):
+ def wirefmt(self, fmtoutfn, fmtinfn, fmtdecfn):
res = ' Wire#(%s) ' % self.bitspec
if self.action:
res += '%s' % fmtinfn(self.name)
single indicates that there is only one of these, and
so the name must *not* be extended numerically (see pname)
"""
+ # sample interface object:
+ """
+ twiinterface_decl = Interface('twi',
+ [{'name': 'sda', 'outen': True},
+ {'name': 'scl', 'outen': True},
+ ])
+ """
def __init__(self, ifacename, pinspecs, ganged=None, single=False):
self.ifacename = ifacename
self.ganged = ganged or {}
- self.pins = []
- self.pinspecs = pinspecs
+ self.pins = [] # a list of instances of class Pin
+ self.pinspecs = pinspecs # a list of dictionary
self.single = single
for p in pinspecs:
_p = {}
if p.get('outen') is True: # special case, generate 3 pins
del _p['outen']
for psuffix in ['out', 'outen', 'in']:
+ # changing the name (like sda) to (twi_sda_out)
_p['name'] = "%s_%s" % (self.pname(p['name']), psuffix)
_p['action'] = psuffix != 'in'
self.pins.append(Pin(**_p))
+ # will look like {'name': 'twi_sda_out', 'action': True}
+ # {'name': 'twi_sda_outen', 'action': True}
+ #{'name': 'twi_sda_in', 'action': False}
+ # NOTice - outen key is removed
else:
_p['name'] = self.pname(p['name'])
self.pins.append(Pin(**_p))
+ # sample interface object:
+ """
+ uartinterface_decl = Interface('uart',
+ [{'name': 'rx'},
+ {'name': 'tx', 'action': True},
+ ])
+ """
+ """
+ getifacetype is called multiple times in actual_pinmux.py
+ x = ifaces.getifacetype(temp), where temp is uart_rx, spi_mosi
+ Purpose is to identify is function : input/output/inout
+ """
+
def getifacetype(self, name):
for p in self.pinspecs:
fname = "%s_%s" % (self.ifacename, p['name'])
interface may be "ganged" together.
"""
if not self.ganged:
- return ''
+ return '' # when self.ganged is None
#print self.ganged
res = []
for (k, pnames) in self.ganged.items():
def wirefmt(self, *args):
res = '\n'.join(map(self.wirefmtpin, self.pins)).format(*args)
res += '\n'
- for p in self.pinspecs:
- name = self.pname(p['name']).format(*args)
- res += " GenericIOType %s_io = GenericIOType{\n" % name
- params = []
- if p.get('outen') is True:
- outname = self.ifacefmtoutfn(name)
- params.append('outputval:%s_out,' % outname)
- params.append('output_en:%s_outen,' % outname) # match busfmt
- params.append('input_en:~%s_outen,' % outname)
- elif p.get('action'):
- outname = self.ifacefmtoutfn(name)
- params.append('outputval:%s,' % outname)
- params.append('output_en:1,')
- params.append('input_en:0,')
- else:
- params.append('outputval:0,')
- params.append('output_en:0,')
- params.append('input_en:1,')
- params += ['pullup_en:0,', 'pulldown_en:0,',
- 'pushpull_en:0,', 'drivestrength:0,',
- 'opendrain_en:0']
- for param in params:
- res += ' %s\n' % param
- res += ' };\n'
return '\n' + res
def ifacefmt(self, *args):
res = '\n'.join(map(self.ifacefmtdecpin, self.pins)).format(*args)
- return '\n' + res
+ return '\n' + res # pins is a list
def ifacefmtdecfn(self, name):
- return name
+ return name # like: uart
def ifacefmtdecfn2(self, name):
- return name
+ return name # like: uart
+
+ def ifacefmtdecfn3(self, name):
+ """ HACK! """
+ return "%s_outen" % name # like uart_outen
def ifacefmtoutfn(self, name):
- return "wr%s" % name
+ return "wr%s" % name # like wruart
def ifacefmtinfn(self, name):
return "wr%s" % name
return pin.ifacefmt(self.ifacefmtdecfn)
def ifacefmtpin(self, pin):
- return pin.ifacedef(self.ifacefmtoutfn, self.ifacefmtinfn,
- self.ifacefmtdecfn2)
+ decfn = self.ifacefmtdecfn2
+ outfn = self.ifacefmtoutfn
+ #print pin, pin.outenmode
+ if pin.outenmode:
+ decfn = self.ifacefmtdecfn3
+ outfn = self.ifacefmtoutenfn
+ return pin.ifacedef(outfn, self.ifacefmtinfn,
+ decfn)
def ifacedef(self, *args):
res = '\n'.join(map(self.ifacefmtpin, self.pins))
class IOInterface(Interface):
+ def ifacefmtoutenfn(self, name):
+ return "cell{0}_mux_outen"
+
def ifacefmtoutfn(self, name):
""" for now strip off io{0}_ part """
return "cell{0}_mux_out"
return generic_io.format(*args)
-class Interfaces(UserDict):
+class Interfaces(InterfacesBase):
""" contains a list of interface definitions
"""
- def __init__(self, pth):
- self.pth = pth
- self.ifacecount = []
- UserDict.__init__(self, {})
- ift = 'interfaces.txt'
- if pth:
- ift = os.path.join(pth, ift)
- with open(ift, 'r') as ifile:
- for ln in ifile.readlines():
- ln = ln.strip()
- ln = ln.split("\t")
- name = ln[0]
- count = int(ln[1])
- spec, ganged = self.read_spec(pth, name)
- iface = Interface(name, spec, ganged, count == 1)
- self.ifaceadd(name, count, iface)
-
- def getifacetype(self, fname):
- # finds the interface type, e.g sd_d0 returns "inout"
- for iface in self.values():
- typ = iface.getifacetype(fname)
- if typ:
- return typ
- return None
-
- def ifaceadd(self, name, count, iface, at=None):
- if at is None:
- at = len(self.ifacecount)
- self.ifacecount.insert(at, (name, count))
- self[name] = iface
-
- def read_spec(self, pth, name):
- spec = []
- ganged = {}
- fname = '%s.txt' % name
- if pth:
- ift = os.path.join(pth, fname)
- with open(ift, 'r') as sfile:
- for ln in sfile.readlines():
- ln = ln.strip()
- ln = ln.split("\t")
- name = ln[0]
- d = {'name': name}
- if ln[1] == 'out':
- d['action'] = True
- elif ln[1] == 'inout':
- d['outen'] = True
- if len(ln) == 3:
- bus = ln[2]
- if bus not in ganged:
- ganged[bus] = []
- ganged[bus].append(name)
- spec.append(d)
- return spec, ganged
+ def __init__(self, pth=None):
+ InterfacesBase.__init__(self, Interface, pth)
def ifacedef(self, f, *args):
for (name, count) in self.ifacecount:
io_interface = IOInterface(
'io',
- [{'name': 'cell', 'enabled': False, 'bitspec': 'GenericIOType'},
- {'name': 'inputval', 'action': True, 'io': True}, ])
+ [{'name': 'cell_out', 'enabled': True, },
+ {'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
+ {'name': 'cell_in', 'action': True, 'io': True}, ])
# == Peripheral Interface definitions == #
# these are the interface of the peripherals to the pin mux
projects / pinmux.git / blobdiff