import types
+def li(txt, indent):
+ indent = ' ' * indent
+ istxt = False
+ if isinstance(txt, str):
+ istxt = True
+ txt = txt.split('\n')
+ res = []
+ for line in txt:
+ line = line.split('\n')
+ res += line
+ txt = res
+ res = []
+ for line in txt:
+ res.append(indent + line)
+ if istxt:
+ res = '\n'.join(res)
+ return res
+
+
class PBase(object):
def __init__(self, name):
self.name = name
def extifdecl(self, name, count):
sname = self.get_iname(count)
- return " interface PeripheralSide%s %s;" % (name.upper(), sname)
+ return "interface PeripheralSide%s %s;" % (name.upper(), sname)
def has_axi_master(self):
return False
+ def irq_name(self):
+ return ""
+
+ def mk_dma_irq(self, name, count):
+ if not self.irq_name():
+ return ''
+ sname = self.get_iname(count)
+ return "{0}_interrupt".format(sname)
+
+ def mk_dma_rule(self, name, count):
+ irqname = self.mk_dma_irq(name, count)
+ if not irqname:
+ return ''
+ pirqname = self.irq_name().format(count)
+ template = " {0}_interrupt.send(\n" + \
+ " slow_peripherals.{1});"
+ return template.format(irqname, pirqname)
+
+ def get_clock_reset(self, name, count):
+ return "slow_clock,slow_reset"
+
+ def mk_dma_sync(self, name, count):
+ irqname = self.mk_dma_irq(name, count)
+ if not irqname:
+ return ''
+ sname = self.peripheral.iname().format(count)
+ template = "SyncBitIfc#(Bit#(1)) {0} <-\n" + \
+ " <-mkSyncBitToCC({1});"
+ return template.format(irqname, self.get_clock_reset(name, count))
+
+ def mk_dma_connect(self, name, count):
+ irqname = self.mk_dma_irq(name, count)
+ if not irqname:
+ return ''
+ return "{0}.read".format(irqname)
+
def fastifdecl(self, name, count):
return ''
bname = self.axibase(name, ifacenum)
bend = self.axiend(name, ifacenum)
name = self.axi_slave_name(name, ifacenum)
- return """\
- if(addr>=`{0} && addr<=`{1})
- return tuple2(True,fromInteger(valueOf({2})));
- else""".format(bname, bend, name)
+ template = """\
+if(addr>=`{0} && addr<=`{1})
+ return tuple2(True,fromInteger(valueOf({2})));
+else"""
+ return template.format(bname, bend, name)
def mk_pincon(self, name, count):
# TODO: really should be using bsv.interface_decl.Interfaces
pname = p['name']
#n = "{0}{1}".format(self.name, self.mksuffix(name, count))
n = name # "{0}{1}".format(self.name, self.mksuffix(name, count))
- ret.append(" //%s %s" % (n, str(p)))
+ ret.append("//%s %s" % (n, str(p)))
sname = self.peripheral.iname().format(count)
sname = "{0}.{1}".format(sname, pname)
ps = "pinmux.peripheral_side.%s" % sname
ps_ = ps + '_out'
else:
ps_ = ps
- ret.append(" mkConnection({0},\n\t\t\t{1}.{2});"
+ ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
.format(ps_, n_, fname))
fname = None
if p.get('outen'):
if isinstance(fname, str):
fname = "{0}.{1}".format(n_, fname)
fname = self.pinname_tweak(pname, 'outen', fname)
- ret.append(" mkConnection({0}_outen,\n\t\t\t{1});"
+ ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
.format(ps, fname))
if typ == 'in' or typ == 'inout':
fname = self.pinname_in(pname)
n_ = "{0}{1}".format(n, count)
n_ = '{0}.{1}'.format(n_, fname)
n_ = self.ifname_tweak(pname, 'in', n_)
- ret.append(" mkConnection({1}, {0});".format(ps_, n_))
+ ret.append(
+ "mkConnection({1},\n\t\t\t{0});".format(
+ ps_, n_))
return '\n'.join(ret)
def mk_cellconn(self, *args):
return i
def __mk_connection(self, con, aname, fabricname):
- txt = " mkConnection ({2}.v_to_slaves\n" + \
- " [fromInteger(valueOf({1}))],\n" + \
- " {0});"
+ txt = "mkConnection ({2}.v_to_slaves\n" + \
+ " [fromInteger(valueOf({1}))],\n" + \
+ " {0});"
print "PBase __mk_connection", self.name, aname
if not con:
return txt.format(con, aname, fabricname)
def __mk_master_connection(self, con, aname):
- txt = " mkConnection (slow_fabric.v_to_slaves\n" + \
- " [fromInteger(valueOf({1}))],\n" + \
- " {0});"
+ txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
+ " [fromInteger(valueOf({1}))],\n" + \
+ " {0});"
print "PBase __mk_connection", self.name, aname
if not con:
if niq == 0:
return ('', irq_offs)
name = self.get_iname(inum)
- res.append(" // PLIC rules for {0}".format(name))
+ res.append("// PLIC rules for {0}".format(name))
for idx in range(niq):
plic_obj = self.plic_object(name, idx)
print "plic_obj", name, idx, plic_obj
def mk_ext_ifacedef(self, iname, inum):
return ''
- def extifinstance(self, name, count):
- sname = self.peripheral.iname().format(count)
+ def extfastifinstance(self, name, count):
+ return ''
+
+ def _extifinstance(self, name, count, suffix, prefix, samename=False,
+ ifsuffix=None):
+ if ifsuffix is None:
+ ifsuffix = ''
pname = self.get_iname(count)
- template = " interface {0} = pinmux.peripheral_side.{1};"
- return template.format(pname, sname)
+ if samename:
+ sname = pname
+ else:
+ sname = self.peripheral.iname().format(count)
+ template = "interface {0}{3} = {2}{1}{4};"
+ return template.format(pname, sname, prefix, suffix, ifsuffix)
+
+ def extifinstance2(self, name, count):
+ return ''
+
+ def extifinstance(self, name, count):
+ return self._extifinstance(name, count, "",
+ "pinmux.peripheral_side.")
mkplic_rule = """\
- rule rl_connect_{0}_to_plic_{2};
- if({1} == 1'b1) begin
- ff_gateway_queue[{2}].enq(1);
- plic.ifc_external_irq[{2}].irq_frm_gateway(True);
- end
- endrule
+rule rl_connect_{0}_to_plic_{2};
+ if({1} == 1'b1) begin
+ ff_gateway_queue[{2}].enq(1);
+ plic.ifc_external_irq[{2}].irq_frm_gateway(True);
+ end
+endrule
"""
-axi_master_declarations= """\
+axi_master_declarations = """\
typedef 0 Dmem_master_num;
typedef 1 Imem_master_num;
{0}
-typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif ) Debug_master_num;
-typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif ) DMA_master_num;
-typedef TAdd#(DMA_master_num,1) Num_Masters;
+typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif )
+ Debug_master_num;
+typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif )
+ DMA_master_num;
+typedef TAdd#(DMA_master_num,1)
+ Num_Masters;
"""
axi_fastslave_declarations = """\
{0}
-typedef TAdd#(LastGen_fastslave_num,1) Sdram_cfg_slave_num;
-typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif ) Sdram_cfg_slave_num;
-typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif ) BootRom_slave_num ;
-typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif ) Debug_slave_num ;
-typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif ) TCM_slave_num;
-typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif ) Dma_slave_num;
+typedef TAdd#(LastGen_fastslave_num,1) Sdram_slave_num;
+typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif )
+ Sdram_cfg_slave_num;
+typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif )
+ BootRom_slave_num ;
+typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif )
+ Debug_slave_num ;
+typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif )
+ TCM_slave_num;
+typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif )
+ Dma_slave_num;
typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
-typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif ) VME_slave_num;
-typedef TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif ) FlexBus_slave_num;
-typedef TAdd#(FlexBus_slave_num,1) Num_Slaves;
+typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif )
+ VME_slave_num;
+typedef TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
+ FlexBus_slave_num;
+typedef TAdd#(FlexBus_slave_num,1)
+ Num_Slaves;
"""
"""
pinmux_cellrule = """\
- rule connect_select_lines_pinmux;
+rule connect_select_lines_pinmux;
{0}
- endrule
+endrule
"""
self.slow = slow(ifacename)
self.slow.peripheral = self
for fname in ['slowimport',
- 'extifinstance', 'extifdecl',
+ 'extfastifinstance',
+ 'extifinstance2', 'extifinstance', 'extifdecl',
'slowifdecl', 'slowifdeclmux',
'fastifdecl',
- 'mkslow_peripheral',
+ 'mkslow_peripheral',
+ 'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
'mkfast_peripheral',
'mk_plic', 'mk_ext_ifacedef',
'mk_connection', 'mk_cellconn', 'mk_pincon']:
for (name, count) in self.ifacecount:
#print "slowimport", name, self.data[name].slowimport
ret.append(self.data[name].slowimport())
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
+
+ def extfastifinstance(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ iname = self.data[name].iname().format(i)
+ print "extfast", iname, self.is_on_fastbus(name, i)
+ if self.is_on_fastbus(name, i):
+ continue
+ ret.append(self.data[name].extfastifinstance(name, i))
+ return '\n'.join(li(list(filter(None, ret)), 8))
+
+ def extifinstance2(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ iname = self.data[name].iname().format(i)
+ ret.append(self.data[name].extifinstance2(name, i))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def extifinstance(self, *args):
ret = []
if not self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].extifinstance(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def extifdecl(self, *args):
ret = []
if not self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].extifdecl(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def slowifdeclmux(self, *args):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
ret.append(self.data[name].slowifdeclmux(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def fastifdecl(self, *args):
ret = []
if self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].fastifdecl(name, i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
def slowifdecl(self, *args):
ret = []
ret.append(self.data[name].slowifdecl().format(i, name))
return '\n'.join(list(filter(None, ret)))
+ def axi_fastmem_def(self, *args):
+ return self._axi_reg_def(0x50000000, *args)
+
def axi_reg_def(self, *args):
+ return self._axi_reg_def(0x00011100, *args)
+
+ def _axi_reg_def(self, start, *args):
ret = []
- start = 0x00011100 # start of AXI peripherals address
for (name, count) in self.ifacecount:
for i in range(count):
if self.is_on_fastbus(name, i):
if self.is_on_fastbus(name, i):
continue
ret.append(self.data[name].axi_addr_map(i))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mkfast_peripheral(self, *args):
ret = []
print name, count, x
suffix = self.data[name].mksuffix(name, i)
ret.append(x.format(suffix))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mkslow_peripheral(self, *args):
ret = []
print name, count, x
suffix = self.data[name].mksuffix(name, i)
ret.append(x.format(suffix))
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mk_fast_connection(self, *args):
ret = []
print "txt", txt
print self.data[name].mk_connection
ret.append(txt)
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 12))
def mk_connection(self, *args):
ret = []
print "txt", txt
print self.data[name].mk_connection
ret.append(txt)
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mk_cellconn(self):
ret = []
continue
(txt, cellcount) = res
ret.append(txt)
- ret = '\n'.join(list(filter(None, ret)))
- return pinmux_cellrule.format(ret)
+ ret = li('\n'.join(list(filter(None, ret))), 4)
+ return li(pinmux_cellrule.format(ret), 4)
def mk_pincon(self):
ret = []
continue
txt = self.data[name].mk_pincon(name, i)
ret.append(txt)
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
+
+ def mk_dma_irq(self):
+ ret = []
+ sync = []
+ rules = []
+ cnct = []
+
+ self.dma_count = 0
+
+ for (name, count) in self.ifacecount:
+ ifacerules = []
+ for i in range(count):
+ if not self.is_on_fastbus(name, i):
+ continue
+ txt = self.data[name].mk_dma_sync(name, i)
+ if txt:
+ self.dma_count += 1
+ sync.append(txt)
+ txt = self.data[name].mk_dma_rule(name, i)
+ ifacerules.append(txt)
+ txt = self.data[name].mk_dma_connect(name, i)
+ cnct.append(txt)
+ ifacerules = list(filter(None, ifacerules))
+ if ifacerules:
+ txt = "rule synchronize_%s_interrupts;" % name
+ rules.append(txt)
+ rules += ifacerules
+ rules.append("endrule")
+
+ cnct = list(filter(None, cnct))
+ ct = self.dma_count
+ _cnct = ["rule rl_connect_interrupt_to_DMA;",
+ " Bit #(%d) lv_interrupt_to_DMA={" % ct]
+ spc = " "
+ spcsep = ",\n" + spc
+ cnct = _cnct + [spc + spcsep.join(cnct)]
+ cnct.append(" };")
+ cnct.append(" dma.interrupt_from_peripherals(\n" +
+ " lv_interrupt_to_DMA);")
+ cnct.append("endrule;")
+
+ ret = list(filter(None, sync + rules + cnct))
+ ret = li(ret, 15)
+ return '\n'.join(ret)
+
+ def num_dmachannels(self):
+ return "`define NUM_DMACHANNELS {0}".format(self.dma_count)
def mk_ext_ifacedef(self):
ret = []
continue
txt = self.data[name].mk_ext_ifacedef(name, i)
ret.append(txt)
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 8))
def mk_plic(self):
ret = []
(txt, irq_offs) = res
ret.append(txt)
self.num_slow_irqs = irq_offs
- return '\n'.join(list(filter(None, ret)))
+ return '\n'.join(li(list(filter(None, ret)), 4))
def mk_sloirqsdef(self):
return " `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
from qspi import qspi, mqspi
from gpio import gpio
from rgbttl import rgbttl
+ from flexbus import flexbus
for k, v in {'uart': uart,
'rs232': rs232,
'sd': sdmmc,
'jtag': jtag,
'lcd': rgbttl,
+ 'fb': flexbus,
'gpio': gpio
}.items():
if name.startswith(k):