if not irqname:
return ''
pirqname = self.irq_name().format(count)
- template = " {0}_interrupt.send(\n" + \
+ template = " {0}.send(\n" + \
" slow_peripherals.{1});"
return template.format(irqname, pirqname)
ret += cn
return '\n'.join(ret)
+ def _mk_vpincon(self, name, count, ptyp, typ, pname, stype=None):
+ if stype is None:
+ stype = pname
+ ret = []
+ ret.append("//%s %s %s %s %s" % (name, ptyp, typ, pname, stype))
+ if ptyp == 'fast':
+ sname = self.get_iname(count)
+ ps = "slow_peripherals.%s" % sname
+ else:
+ sname = self.peripheral.iname().format(count)
+ ps = "pinmux.peripheral_side.%s" % sname
+ n = self.get_iname(count)
+ if typ == 'in':
+ n = "{0}.{1}".format(n, stype)
+ ps_ = "{0}.{1}".format(ps, pname)
+ ret += self._mk_actual_connection(typ, name, count, typ,
+ pname, ps_, n, stype)
+ return '\n'.join(ret)
+
def _mk_actual_connection(self, ctype, name, count, typ,
pname, ps, n, fname):
ret = []
sync, n))
return ret
- def mk_clk_con(self, name, count):
+
+ def _mk_clk_con(self, name, count, ctype):
ret = []
ck = self.get_clock_reset(name, count)
if ck == PBase.get_clock_reset(self, name, count):
return ''
- spc = "sp_clock, sp_reset"
+ if ctype == 'slow':
+ spc = self.get_clk_spc(ctype)
+ else:
+ spc = ck
+ ck = self.get_clk_spc(ctype)
template = """\
Ifc_sync#({0}) {1}_sync <-mksyncconnection(
{2}, {3});"""
pname = p['name']
n = name
if typ == 'out' or typ == 'inout':
+ fname = self.pinname_out(pname)
+ if not fname:
+ continue
if not n.startswith('gpio'): # XXX EURGH! horrible hack
n_ = "{0}{1}".format(n, count)
else:
n_ = '{0}_{1}'.format(n_, pname)
ret.append(template.format("Bit#(1)", n_, ck, spc))
if typ == 'in' or typ == 'inout':
+ fname = self.pinname_in(pname)
+ if not fname:
+ continue
#fname = self.pinname_in(pname)
n_ = "{0}{1}".format(n, count)
n_ = '{0}_{1}'.format(n_, pname)
ret.append(template.format("Bit#(1)", n_, spc, ck))
return '\n'.join(ret)
+ def get_clk_spc(self, ctype):
+ if ctype == 'slow':
+ return "sp_clock, sp_reset"
+ else:
+ return "core_clock, core_reset"
+
+ def _mk_clk_vcon(self, name, count, ctype, typ, pname, bitspec):
+ ck = self.get_clock_reset(name, count)
+ if ck == PBase.get_clock_reset(self, name, count):
+ return ''
+ if ctype == 'slow':
+ spc = self.get_clk_spc(ctype)
+ else:
+ spc = ck
+ ck = self.get_clk_spc(ctype)
+ template = """\
+Ifc_sync#({0}) {1}_sync <-mksyncconnection(
+ {2}, {3});"""
+
+ n_ = "{0}{1}".format(name, count)
+ n_ = '{0}_{1}'.format(n_, pname)
+ if typ == 'in' or typ == 'inout':
+ ck, spc = spc, ck
+ return template.format(bitspec, n_, ck, spc)
+
def mk_cellconn(self, *args):
return ''
return ''
return txt.format(con, aname, fabricname)
- def __mk_master_connection(self, con, aname):
- txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
- " [fromInteger(valueOf({1}))],\n" + \
- " {0});"
+ def __mk_master_connection(self, con, aname, fabricname):
+ txt = "mkConnection ({0}, {2}.v_from_masters\n" + \
+ " [fromInteger(valueOf({1}))]);\n"
- print "PBase __mk_connection", self.name, aname
+ print "PBase __mk_master_connection", self.name, aname
if not con:
return ''
- return txt.format(con, aname)
+ return txt.format(con, aname, fabricname)
+
+ def mk_master_connection(self, count, fabricname, typ, name=None):
+ if not self.has_axi_master():
+ return ''
+ if name is None:
+ name = self.name
+ print "PBase mk_master_conn", self.name, count
+ aname = self.axi_master_name(name, count, typ)
+ con = self._mk_connection(name, count, True).format(count, aname)
+ return self.__mk_master_connection(con, aname, fabricname)
def mk_connection(self, count, fabricname, typ, name=None):
if name is None:
name = self.name
print "PBase mk_conn", self.name, count
aname = self.axi_slave_name(name, count, typ)
- #dname = self.mksuffix(name, count)
- #dname = "{0}{1}".format(name, dname)
con = self._mk_connection(name, count).format(count, aname)
return self.__mk_connection(con, aname, fabricname)
'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
'mkfast_peripheral',
'mk_plic', 'mk_ext_ifacedef',
- 'mk_clk_con', 'mk_ext_ifacedef',
- 'mk_connection', 'mk_cellconn', '_mk_pincon']:
+ '_mk_clk_con', 'mk_ext_ifacedef',
+ 'mk_connection', 'mk_master_connection',
+ 'mk_cellconn', '_mk_pincon']:
fn = CallFn(self, fname)
setattr(self, fname, types.MethodType(fn, self))
ret.append(x.format(suffix))
return '\n'.join(li(list(filter(None, ret)), 8))
- def mk_fast_connection(self, *args):
+ def _mk_connection(self, fabric, typ, indent, master, *args):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
if self.is_on_fastbus(name, i):
continue
- txt = self.data[name].mk_connection(i, "fabric", "fast")
+ if master:
+ txt = self.data[name].mk_master_connection(i, fabric, typ)
+ else:
+ txt = self.data[name].mk_connection(i, fabric, typ)
if name == 'gpioa':
print "txt", txt
- print self.data[name].mk_connection
ret.append(txt)
- return '\n'.join(li(list(filter(None, ret)), 12))
+ return '\n'.join(li(list(filter(None, ret)), indent))
+
+ def mk_master_connection(self, *args):
+ return self._mk_connection("fabric", "fast", 8, True, *args)
+
+ def mk_fast_connection(self, *args):
+ return self._mk_connection("fabric", "fast", 12, False, *args)
def mk_connection(self, *args):
- ret = []
- for (name, count) in self.ifacecount:
- for i in range(count):
- if self.is_on_fastbus(name, i):
- continue
- txt = self.data[name].mk_connection(i, "slow_fabric", "")
- if name == 'gpioa':
- print "txt", txt
- print self.data[name].mk_connection
- ret.append(txt)
- return '\n'.join(li(list(filter(None, ret)), 8))
+ return self._mk_connection("slow_fabric", "", 8, False, *args)
def mk_cellconn(self):
ret = []
def mk_sloirqsdef(self):
return " `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
- def mk_clk_con(self):
+ def mk_fastclk_con(self):
+ return self._mk_clk_con("fast")
+
+ def mk_slowclk_con(self):
+ return self._mk_clk_con("slow")
+
+ def _mk_clk_con(self, ctype):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
if self.is_on_fastbus(name, i):
continue
- txt = self.data[name].mk_clk_con(name, i)
+ txt = self.data[name]._mk_clk_con(name, i, ctype)
ret.append(txt)
return '\n'.join(li(list(filter(None, ret)), 8))
from gpio import gpio
from rgbttl import rgbttl
from flexbus import flexbus
+ from sdram import sdram
for k, v in {'uart': uart,
'rs232': rs232,
'twi': twi,
+ 'sdr': sdram,
'quart': quart,
'mqspi': mqspi,
'mspi': mspi,
'spi': spi,
'pwm': pwm,
'eint': eint,
- 'sd': sdmmc,
+ 'mmc': sdmmc,
'jtag': jtag,
'lcd': rgbttl,
'fb': flexbus,