sort out flexbus vector pincon

[pinmux.git] / src / bsv / peripheral_gen / base.py

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index f6d11f1146b1016fe916cb64a5fb5a1e9df6b6a7..72385cf2b5f5f26f5b3e33ae59b9dd8a23fd4145 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -45,7 +45,7 @@ class PBase(object):
         if not irqname:
             return ''
         pirqname = self.irq_name().format(count)
-        template = "   {0}_interrupt.send(\n" + \
+        template = "   {0}.send(\n" + \
                    "           slow_peripherals.{1});"
         return template.format(irqname, pirqname)
 
@@ -196,35 +196,65 @@ else"""
                     ret += cn
         return '\n'.join(ret)
 
+    def _mk_vpincon(self, name, count, ptyp, typ, pname, stype=None):
+        if stype is None:
+            stype = pname
+        ret = []
+        if ptyp == 'fast':
+            sname = self.get_iname(count)
+            ps = "slow_peripherals.%s" % sname
+        else:
+            sname = self.peripheral.iname().format(count)
+            ps = "pinmux.peripheral_side.%s" % sname
+        n = self.get_iname(count)
+        ps_ = "{0}.{1}".format(ps, pname)
+        ret += self._mk_actual_connection(typ, name, count, typ,
+                                          pname, ps_, n, stype)
+        return '\n'.join(ret)
+
     def _mk_actual_connection(self, ctype, name, count, typ,
                               pname, ps, n, fname):
         ret = []
+        ck = self.get_clock_reset(name, count)
         if ctype == 'out':
-            ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
-                       .format(ps, n, fname))
+            if ck == PBase.get_clock_reset(self, name, count):
+                ret.append("mkConnection({0},\n\t\t\t{1}.{2});"
+                           .format(ps, n, fname))
+            else:
+                n2 = "{0}{1}".format(name, count)
+                sync = '{0}_{1}_sync'.format(n2, pname)
+                ret.append("mkConnection({0},\n\t\t\t{1}.get);"
+                           .format(ps, sync))
+                ret.append("mkConnection({0}.put,\n\t\t\t{1}.{2});"
+                           .format(sync, n, fname))
         elif ctype == 'outen':
             ret.append("mkConnection({0}_outen,\n\t\t\t{1});"
                        .format(ps, fname))
         elif ctype == 'in':
-            ck = self.get_clock_reset(name, count)
             if ck == PBase.get_clock_reset(self, name, count):
                 ret.append("mkConnection({1},\n\t\t\t{0});".format(
                             ps, n))
             else:
                 n2 = "{0}{1}".format(name, count)
                 sync = '{0}_{1}_sync'.format(n2, pname)
+                n = "{0}.{1}".format(n, fname)
                 ret.append("mkConnection({1}.put,\n\t\t\t{0});".format(
                             ps, sync))
                 ret.append("mkConnection({1},\n\t\t\t{0}.get);".format(
                             sync, n))
         return ret
 
-    def mk_clk_con(self, name, count):
+
+    def _mk_clk_con(self, name, count, ctype):
         ret = []
         ck = self.get_clock_reset(name, count)
         if ck == PBase.get_clock_reset(self, name, count):
             return ''
-        spc = "sp_clock, sp_reset"
+        if ctype == 'slow':
+            spc = "sp_clock, sp_reset"
+        else:
+            spc = ck
+            ck = "core_clock, core_reset"
         template = """\
 Ifc_sync#({0}) {1}_sync <-mksyncconnection(
             {2}, {3});"""
@@ -232,7 +262,20 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
             typ = p['type']
             pname = p['name']
             n = name  
+            if typ == 'out' or typ == 'inout':
+                fname = self.pinname_out(pname)
+                if not fname:
+                    continue
+                if not n.startswith('gpio'):  # XXX EURGH! horrible hack
+                    n_ = "{0}{1}".format(n, count)
+                else:
+                    n_ = n
+                n_ = '{0}_{1}'.format(n_, pname)
+                ret.append(template.format("Bit#(1)", n_, ck, spc))
             if typ == 'in' or typ == 'inout':
+                fname = self.pinname_in(pname)
+                if not fname:
+                    continue
                 #fname = self.pinname_in(pname)
                 n_ = "{0}{1}".format(n, count)
                 n_ = '{0}_{1}'.format(n_, pname)
@@ -240,6 +283,23 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection(
                 ret.append(template.format("Bit#(1)", n_, spc, ck))
         return '\n'.join(ret)
 
+    def _mk_clk_vcon(self, name, count, ctype, typ, pname, bitspec):
+        ck = self.get_clock_reset(name, count)
+        if ck == PBase.get_clock_reset(self, name, count):
+            return ''
+        if ctype == 'slow':
+            spc = "sp_clock, sp_reset"
+        else:
+            spc = ck
+            ck = "core_clock, core_reset"
+        template = """\
+Ifc_sync#({0}) {1}_sync <-mksyncconnection(
+            {2}, {3});"""
+
+        n_ = "{0}{1}".format(name, count)
+        n_ = '{0}_{1}'.format(n_, pname)
+        return template.format(bitspec,  n_, ck, spc)
+
 
     def mk_cellconn(self, *args):
         return ''
@@ -434,7 +494,7 @@ class PeripheralIface(object):
                       'mk_dma_sync', 'mk_dma_connect', 'mk_dma_rule',
                       'mkfast_peripheral',
                       'mk_plic', 'mk_ext_ifacedef',
-                      'mk_clk_con', 'mk_ext_ifacedef',
+                      '_mk_clk_con', 'mk_ext_ifacedef',
                       'mk_connection', 'mk_cellconn', '_mk_pincon']:
             fn = CallFn(self, fname)
             setattr(self, fname, types.MethodType(fn, self))
@@ -777,13 +837,19 @@ class PeripheralInterfaces(object):
     def mk_sloirqsdef(self):
         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
 
-    def mk_clk_con(self):
+    def mk_fastclk_con(self):
+        return self._mk_clk_con("fast")
+
+    def mk_slowclk_con(self):
+        return self._mk_clk_con("slow")
+
+    def _mk_clk_con(self, ctype):
         ret = []
         for (name, count) in self.ifacecount:
             for i in range(count):
                 if self.is_on_fastbus(name, i):
                     continue
-                txt = self.data[name].mk_clk_con(name, i)
+                txt = self.data[name]._mk_clk_con(name, i, ctype)
                 ret.append(txt)
         return '\n'.join(li(list(filter(None, ret)), 8))