fix fast slave bus index names

[pinmux.git] / src / bsv / peripheral_gen / base.py

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 3e6fbde0209d888a7eb1db0aca14bd92a656151e..c62a492a2451241207940f5fc213185a265c4626 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -1,5 +1,6 @@
 import types
 
+
 def li(txt, indent):
     indent = ' ' * indent
     istxt = False
@@ -121,14 +122,18 @@ class PBase(object):
         name = self.axi_slave_name(name, ifacenum, typ)
         return ("typedef {0} {1};".format(idx, name), 1)
 
-    def axi_addr_map(self, name, ifacenum):
+    def axi_fastaddr_map(self, name, ifacenum):
+        return self.axi_addr_map(name, ifacenum, 'fast')
+
+    def axi_addr_map(self, name, ifacenum, typ=""):
         bname = self.axibase(name, ifacenum)
         bend = self.axiend(name, ifacenum)
-        name = self.axi_slave_name(name, ifacenum)
-        return """\
-        if(addr>=`{0} && addr<=`{1})
-            return tuple2(True,fromInteger(valueOf({2})));
-        else""".format(bname, bend, name)
+        name = self.axi_slave_name(name, ifacenum, typ)
+        template = """\
+if(addr>=`{0} && addr<=`{1})
+    return tuple2(True,fromInteger(valueOf({2})));
+else"""
+        return template.format(bname, bend, name)
 
     def mk_pincon(self, name, count):
         # TODO: really should be using bsv.interface_decl.Interfaces
@@ -140,7 +145,7 @@ class PBase(object):
             pname = p['name']
             #n = "{0}{1}".format(self.name, self.mksuffix(name, count))
             n = name  # "{0}{1}".format(self.name, self.mksuffix(name, count))
-            ret.append("    //%s %s" % (n, str(p)))
+            ret.append("//%s %s" % (n, str(p)))
             sname = self.peripheral.iname().format(count)
             sname = "{0}.{1}".format(sname, pname)
             ps = "pinmux.peripheral_side.%s" % sname
@@ -176,8 +181,10 @@ class PBase(object):
                     n_ = "{0}{1}".format(n, count)
                     n_ = '{0}.{1}'.format(n_, fname)
                     n_ = self.ifname_tweak(pname, 'in', n_)
-                    ret.append("mkConnection({1}, {0});".format(ps_, n_))
-        return '\n'.join(li(ret, 6))
+                    ret.append(
+                        "mkConnection({1},\n\t\t\t{0});".format(
+                            ps_, n_))
+        return '\n'.join(ret)
 
     def mk_cellconn(self, *args):
         return ''
@@ -199,7 +206,7 @@ class PBase(object):
         print "PBase __mk_connection", self.name, aname
         if not con:
             return ''
-        return li(txt.format(con, aname, fabricname), 8)
+        return txt.format(con, aname, fabricname)
 
     def __mk_master_connection(self, con, aname):
         txt = "mkConnection (slow_fabric.v_to_slaves\n" + \
@@ -209,7 +216,7 @@ class PBase(object):
         print "PBase __mk_connection", self.name, aname
         if not con:
             return ''
-        return li(txt.format(con, aname), 8)
+        return txt.format(con, aname)
 
     def mk_connection(self, count, fabricname, typ, name=None):
         if name is None:
@@ -256,7 +263,7 @@ class PBase(object):
             plic = mkplic_rule.format(name, plic_obj, irq_offs)
             res.append(plic)
             irq_offs += 1  # increment to next irq
-        return ('\n'.join(li(res, 5)), irq_offs)
+        return ('\n'.join(res), irq_offs)
 
     def mk_ext_ifacedef(self, iname, inum):
         return ''
@@ -264,21 +271,24 @@ class PBase(object):
     def extfastifinstance(self, name, count):
         return ''
 
-    def _extifinstance(self, name, count, suffix, prefix, samename=False):
+    def _extifinstance(self, name, count, suffix, prefix, samename=False,
+                       ifsuffix=None):
+        if ifsuffix is None:
+            ifsuffix = ''
         pname = self.get_iname(count)
         if samename:
             sname = pname
         else:
             sname = self.peripheral.iname().format(count)
-        template = "        interface {0}{3} = {2}{1};"
-        return template.format(pname, sname, prefix, suffix)
+        template = "interface {0}{3} = {2}{1}{4};"
+        return template.format(pname, sname, prefix, suffix, ifsuffix)
 
     def extifinstance2(self, name, count):
         return ''
 
     def extifinstance(self, name, count):
         return self._extifinstance(name, count, "",
-                                            "pinmux.peripheral_side.")
+                                   "pinmux.peripheral_side.")
 
 
 mkplic_rule = """\
@@ -290,7 +300,7 @@ rule rl_connect_{0}_to_plic_{2};
 endrule
 """
 
-axi_master_declarations= """\
+axi_master_declarations = """\
 typedef 0 Dmem_master_num;
 typedef 1 Imem_master_num;
 {0}
@@ -304,7 +314,7 @@ typedef TAdd#(DMA_master_num,1)
 
 axi_fastslave_declarations = """\
 {0}
-typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_cfg_slave_num;
+typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_slave_num;
 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
                       Sdram_cfg_slave_num;
 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
@@ -313,16 +323,12 @@ typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
                 Debug_slave_num ;
 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
                 TCM_slave_num;
-typedef  TAdd#(TCM_slave_num     ,`ifdef DMA            1 `else 0 `endif )
+typedef  TAdd#(TCM_slave_num     ,`ifdef DMA        1 `else 0 `endif )
                 Dma_slave_num;
 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
                 VME_slave_num;
-typedef  TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
-                FlexBus_slave_num;
-typedef TAdd#(FlexBus_slave_num,1)
-                Num_Slaves;
-
+typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
 """
 
 axi_slave_declarations = """\
@@ -338,9 +344,9 @@ typedef TAdd#(AxiExp1_slave_num,1) Num_Slow_Slaves;
 """
 
 pinmux_cellrule = """\
-    rule connect_select_lines_pinmux;
+rule connect_select_lines_pinmux;
 {0}
-    endrule
+endrule
 """
 
 
@@ -400,6 +406,11 @@ class PeripheralIface(object):
             return ('', 0)
         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 
+    def axi_fastaddr_map(self, count):
+        if not self.slow:
+            return ''
+        return self.slow.axi_fastaddr_map(self.ifacename, count)
+
     def axi_addr_map(self, count):
         if not self.slow:
             return ''
@@ -415,7 +426,7 @@ class PeripheralInterfaces(object):
         for (name, count) in self.ifacecount:
             #print "slowimport", name, self.data[name].slowimport
             ret.append(self.data[name].slowimport())
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 4))
 
     def extfastifinstance(self, *args):
         ret = []
@@ -426,7 +437,7 @@ class PeripheralInterfaces(object):
                 if self.is_on_fastbus(name, i):
                     continue
                 ret.append(self.data[name].extfastifinstance(name, i))
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def extifinstance2(self, *args):
         ret = []
@@ -434,7 +445,7 @@ class PeripheralInterfaces(object):
             for i in range(count):
                 iname = self.data[name].iname().format(i)
                 ret.append(self.data[name].extifinstance2(name, i))
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def extifinstance(self, *args):
         ret = []
@@ -444,7 +455,7 @@ class PeripheralInterfaces(object):
                 if not self.is_on_fastbus(name, i):
                     continue
                 ret.append(self.data[name].extifinstance(name, i))
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def extifdecl(self, *args):
         ret = []
@@ -460,7 +471,7 @@ class PeripheralInterfaces(object):
         for (name, count) in self.ifacecount:
             for i in range(count):
                 ret.append(self.data[name].slowifdeclmux(name, i))
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def fastifdecl(self, *args):
         ret = []
@@ -470,7 +481,7 @@ class PeripheralInterfaces(object):
                 if self.is_on_fastbus(name, i):
                     continue
                 ret.append(self.data[name].fastifdecl(name, i))
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 4))
 
     def slowifdecl(self, *args):
         ret = []
@@ -481,9 +492,14 @@ class PeripheralInterfaces(object):
                 ret.append(self.data[name].slowifdecl().format(i, name))
         return '\n'.join(list(filter(None, ret)))
 
+    def axi_fastmem_def(self, *args):
+        return self._axi_reg_def(0x50000000, *args)
+
     def axi_reg_def(self, *args):
+        return self._axi_reg_def(0x00011100, *args)
+
+    def _axi_reg_def(self, start, *args):
         ret = []
-        start = 0x00011100  # start of AXI peripherals address
         for (name, count) in self.ifacecount:
             for i in range(count):
                 if self.is_on_fastbus(name, i):
@@ -529,6 +545,15 @@ class PeripheralInterfaces(object):
         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
                                  'fast', *args)
 
+    def axi_fastaddr_map(self, *args):
+        ret = []
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                if self.is_on_fastbus(name, i):
+                    continue
+                ret.append(self.data[name].axi_fastaddr_map(i))
+        return '\n'.join(li(list(filter(None, ret)), 8))
+
     def axi_addr_map(self, *args):
         ret = []
         for (name, count) in self.ifacecount:
@@ -536,7 +561,7 @@ class PeripheralInterfaces(object):
                 if self.is_on_fastbus(name, i):
                     continue
                 ret.append(self.data[name].axi_addr_map(i))
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def mkfast_peripheral(self, *args):
         ret = []
@@ -549,7 +574,7 @@ class PeripheralInterfaces(object):
                 print name, count, x
                 suffix = self.data[name].mksuffix(name, i)
                 ret.append(x.format(suffix))
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def mkslow_peripheral(self, *args):
         ret = []
@@ -562,7 +587,7 @@ class PeripheralInterfaces(object):
                 print name, count, x
                 suffix = self.data[name].mksuffix(name, i)
                 ret.append(x.format(suffix))
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def mk_fast_connection(self, *args):
         ret = []
@@ -575,7 +600,7 @@ class PeripheralInterfaces(object):
                     print "txt", txt
                     print self.data[name].mk_connection
                 ret.append(txt)
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 12))
 
     def mk_connection(self, *args):
         ret = []
@@ -588,7 +613,7 @@ class PeripheralInterfaces(object):
                     print "txt", txt
                     print self.data[name].mk_connection
                 ret.append(txt)
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def mk_cellconn(self):
         ret = []
@@ -602,8 +627,8 @@ class PeripheralInterfaces(object):
                     continue
                 (txt, cellcount) = res
                 ret.append(txt)
-        ret = '\n'.join(list(filter(None, ret)))
-        return pinmux_cellrule.format(ret)
+        ret = li('\n'.join(list(filter(None, ret))), 4)
+        return li(pinmux_cellrule.format(ret), 4)
 
     def mk_pincon(self):
         ret = []
@@ -613,7 +638,7 @@ class PeripheralInterfaces(object):
                     continue
                 txt = self.data[name].mk_pincon(name, i)
                 ret.append(txt)
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 4))
 
     def mk_dma_irq(self):
         ret = []
@@ -645,13 +670,13 @@ class PeripheralInterfaces(object):
 
         cnct = list(filter(None, cnct))
         ct = self.dma_count
-        _cnct    = ["rule rl_connect_interrupt_to_DMA;",
-                    "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
+        _cnct = ["rule rl_connect_interrupt_to_DMA;",
+                 "  Bit #(%d) lv_interrupt_to_DMA={" % ct]
         spc = "                      "
         spcsep = ",\n" + spc
         cnct = _cnct + [spc + spcsep.join(cnct)]
         cnct.append("   };")
-        cnct.append("   dma.interrupt_from_peripherals(\n" + \
+        cnct.append("   dma.interrupt_from_peripherals(\n" +
                     "       lv_interrupt_to_DMA);")
         cnct.append("endrule;")
 
@@ -670,7 +695,7 @@ class PeripheralInterfaces(object):
                     continue
                 txt = self.data[name].mk_ext_ifacedef(name, i)
                 ret.append(txt)
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 8))
 
     def mk_plic(self):
         ret = []
@@ -685,7 +710,7 @@ class PeripheralInterfaces(object):
                 (txt, irq_offs) = res
                 ret.append(txt)
         self.num_slow_irqs = irq_offs
-        return '\n'.join(list(filter(None, ret)))
+        return '\n'.join(li(list(filter(None, ret)), 4))
 
     def mk_sloirqsdef(self):
         return "    `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
@@ -713,6 +738,7 @@ class PFactory(object):
         from qspi import qspi, mqspi
         from gpio import gpio
         from rgbttl import rgbttl
+        from flexbus import flexbus
 
         for k, v in {'uart': uart,
                      'rs232': rs232,
@@ -727,6 +753,7 @@ class PFactory(object):
                      'sd': sdmmc,
                      'jtag': jtag,
                      'lcd': rgbttl,
+                     'fb': flexbus,
                      'gpio': gpio
                      }.items():
             if name.startswith(k):