fix fast slave bus index names
[pinmux.git] / src / bsv / peripheral_gen / base.py
index caad20f510c8ea4fb4d708953f3002cc28d05dc0..c62a492a2451241207940f5fc213185a265c4626 100644 (file)
@@ -122,10 +122,13 @@ class PBase(object):
         name = self.axi_slave_name(name, ifacenum, typ)
         return ("typedef {0} {1};".format(idx, name), 1)
 
-    def axi_addr_map(self, name, ifacenum):
+    def axi_fastaddr_map(self, name, ifacenum):
+        return self.axi_addr_map(name, ifacenum, 'fast')
+
+    def axi_addr_map(self, name, ifacenum, typ=""):
         bname = self.axibase(name, ifacenum)
         bend = self.axiend(name, ifacenum)
-        name = self.axi_slave_name(name, ifacenum)
+        name = self.axi_slave_name(name, ifacenum, typ)
         template = """\
 if(addr>=`{0} && addr<=`{1})
     return tuple2(True,fromInteger(valueOf({2})));
@@ -178,7 +181,9 @@ else"""
                     n_ = "{0}{1}".format(n, count)
                     n_ = '{0}.{1}'.format(n_, fname)
                     n_ = self.ifname_tweak(pname, 'in', n_)
-                    ret.append("mkConnection({1},\n\t\t\t{0});".format(ps_, n_))
+                    ret.append(
+                        "mkConnection({1},\n\t\t\t{0});".format(
+                            ps_, n_))
         return '\n'.join(ret)
 
     def mk_cellconn(self, *args):
@@ -266,14 +271,17 @@ else"""
     def extfastifinstance(self, name, count):
         return ''
 
-    def _extifinstance(self, name, count, suffix, prefix, samename=False):
+    def _extifinstance(self, name, count, suffix, prefix, samename=False,
+                       ifsuffix=None):
+        if ifsuffix is None:
+            ifsuffix = ''
         pname = self.get_iname(count)
         if samename:
             sname = pname
         else:
             sname = self.peripheral.iname().format(count)
-        template = "interface {0}{3} = {2}{1};"
-        return template.format(pname, sname, prefix, suffix)
+        template = "interface {0}{3} = {2}{1}{4};"
+        return template.format(pname, sname, prefix, suffix, ifsuffix)
 
     def extifinstance2(self, name, count):
         return ''
@@ -306,7 +314,7 @@ typedef TAdd#(DMA_master_num,1)
 
 axi_fastslave_declarations = """\
 {0}
-typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_cfg_slave_num;
+typedef  TAdd#(LastGen_fastslave_num,1)      Sdram_slave_num;
 typedef  TAdd#(Sdram_slave_num   ,`ifdef SDRAM      1 `else 0 `endif )
                       Sdram_cfg_slave_num;
 typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM    1 `else 0 `endif )
@@ -315,16 +323,12 @@ typedef TAdd#(BootRom_slave_num  ,`ifdef Debug      1 `else 0 `endif )
                 Debug_slave_num ;
 typedef  TAdd#(Debug_slave_num   , `ifdef TCMemory  1 `else 0 `endif )
                 TCM_slave_num;
-typedef  TAdd#(TCM_slave_num     ,`ifdef DMA            1 `else 0 `endif )
+typedef  TAdd#(TCM_slave_num     ,`ifdef DMA        1 `else 0 `endif )
                 Dma_slave_num;
 typedef  TAdd#(Dma_slave_num      ,1 )      SlowPeripheral_slave_num;
 typedef  TAdd#(SlowPeripheral_slave_num,`ifdef VME  1 `else 0 `endif )
                 VME_slave_num;
-typedef  TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif )
-                FlexBus_slave_num;
-typedef TAdd#(FlexBus_slave_num,1)
-                Num_Slaves;
-
+typedef TAdd#(VME_slave_num,1) Num_Fast_Slaves;
 """
 
 axi_slave_declarations = """\
@@ -402,6 +406,11 @@ class PeripheralIface(object):
             return ('', 0)
         return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
 
+    def axi_fastaddr_map(self, count):
+        if not self.slow:
+            return ''
+        return self.slow.axi_fastaddr_map(self.ifacename, count)
+
     def axi_addr_map(self, count):
         if not self.slow:
             return ''
@@ -483,9 +492,14 @@ class PeripheralInterfaces(object):
                 ret.append(self.data[name].slowifdecl().format(i, name))
         return '\n'.join(list(filter(None, ret)))
 
+    def axi_fastmem_def(self, *args):
+        return self._axi_reg_def(0x50000000, *args)
+
     def axi_reg_def(self, *args):
+        return self._axi_reg_def(0x00011100, *args)
+
+    def _axi_reg_def(self, start, *args):
         ret = []
-        start = 0x00011100  # start of AXI peripherals address
         for (name, count) in self.ifacecount:
             for i in range(count):
                 if self.is_on_fastbus(name, i):
@@ -531,6 +545,15 @@ class PeripheralInterfaces(object):
         return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
                                  'fast', *args)
 
+    def axi_fastaddr_map(self, *args):
+        ret = []
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                if self.is_on_fastbus(name, i):
+                    continue
+                ret.append(self.data[name].axi_fastaddr_map(i))
+        return '\n'.join(li(list(filter(None, ret)), 8))
+
     def axi_addr_map(self, *args):
         ret = []
         for (name, count) in self.ifacecount:
@@ -715,6 +738,7 @@ class PFactory(object):
         from qspi import qspi, mqspi
         from gpio import gpio
         from rgbttl import rgbttl
+        from flexbus import flexbus
 
         for k, v in {'uart': uart,
                      'rs232': rs232,
@@ -729,6 +753,7 @@ class PFactory(object):
                      'sd': sdmmc,
                      'jtag': jtag,
                      'lcd': rgbttl,
+                     'fb': flexbus,
                      'gpio': gpio
                      }.items():
             if name.startswith(k):