import types
+
class PBase(object):
def __init__(self, name):
self.name = name
- def slowifdeclmux(self):
- return ''
+ def extifdecl(self, name, count):
+ sname = self.get_iname(count)
+ return " interface PeripheralSide%s %s;" % (name.upper(), sname)
- def slowifinstance(self):
+ def has_axi_master(self):
+ return False
+
+ def slowifdeclmux(self, name, count):
return ''
def slowimport(self):
" `define %(bend)s 'h%(end)08X // %(comment)s" % locals(),
offs)
- def axi_slave_name(self, name, ifacenum):
+ def axi_master_name(self, name, ifacenum, typ=''):
name = name.upper()
- return "{0}{1}_slave_num".format(name, ifacenum)
+ return "{0}{1}_master_num".format(name, ifacenum)
- def axi_slave_idx(self, idx, name, ifacenum):
- name = self.axi_slave_name(name, ifacenum)
+ def axi_slave_name(self, name, ifacenum, typ=''):
+ name = name.upper()
+ return "{0}{1}_{2}slave_num".format(name, ifacenum, typ)
+
+ def axi_master_idx(self, idx, name, ifacenum, typ):
+ name = self.axi_master_name(name, ifacenum, typ)
+ return ("typedef {0} {1};".format(idx, name), 1)
+
+ def axi_slave_idx(self, idx, name, ifacenum, typ):
+ name = self.axi_slave_name(name, ifacenum, typ)
return ("typedef {0} {1};".format(idx, name), 1)
def axi_addr_map(self, name, ifacenum):
#n = "{0}{1}".format(self.name, self.mksuffix(name, count))
n = name # "{0}{1}".format(self.name, self.mksuffix(name, count))
ret.append(" //%s %s" % (n, str(p)))
- sname = self.peripheral.pname(pname).format(count)
+ sname = self.peripheral.iname().format(count)
+ sname = "{0}.{1}".format(sname, pname)
ps = "pinmux.peripheral_side.%s" % sname
if typ == 'out' or typ == 'inout':
- ret.append(" rule con_%s%d_%s_out;" % (name, count, pname))
fname = self.pinname_out(pname)
if not n.startswith('gpio'): # XXX EURGH! horrible hack
n_ = "{0}{1}".format(n, count)
ps_ = ps + '_out'
else:
ps_ = ps
- ret.append(" {0}({1}.{2});".format(ps_, n_, fname))
+ ret.append(" mkConnection({0},\n\t\t\t{1}.{2});"
+ .format(ps_, n_, fname))
fname = None
if p.get('outen'):
fname = self.pinname_outen(pname)
if isinstance(fname, str):
fname = "{0}.{1}".format(n_, fname)
fname = self.pinname_tweak(pname, 'outen', fname)
- ret.append(" {0}_outen({1});".format(ps, fname))
- ret.append(" endrule")
+ ret.append(" mkConnection({0}_outen,\n\t\t\t{1});"
+ .format(ps, fname))
if typ == 'in' or typ == 'inout':
fname = self.pinname_in(pname)
if fname:
ps_ = ps + '_in'
else:
ps_ = ps
- ret.append(
- " rule con_%s%d_%s_in;" %
- (name, count, pname))
n_ = "{0}{1}".format(n, count)
n_ = '{0}.{1}'.format(n_, fname)
n_ = self.ifname_tweak(pname, 'in', n_)
- ret.append(" {1}({0});".format(ps_, n_))
- ret.append(" endrule")
+ ret.append(" mkConnection({1}, {0});".format(ps_, n_))
return '\n'.join(ret)
def mk_cellconn(self, *args):
return ''
+ def mkfast_peripheral(self, size=0):
+ return ''
+
def mkslow_peripheral(self, size=0):
return ''
print "plic_obj", name, idx, plic_obj
plic = mkplic_rule.format(name, plic_obj, irq_offs)
res.append(plic)
- irq_offs += 1 # increment to next irq
+ irq_offs += 1 # increment to next irq
return ('\n'.join(res), irq_offs)
def mk_ext_ifacedef(self, iname, inum):
return ''
+ def extifinstance(self, name, count):
+ sname = self.peripheral.iname().format(count)
+ pname = self.get_iname(count)
+ template = " interface {0} = pinmux.peripheral_side.{1};"
+ return template.format(pname, sname)
+
mkplic_rule = """\
rule rl_connect_{0}_to_plic_{2};
endrule
"""
+axi_master_declarations= """\
+typedef 0 Dmem_master_num;
+typedef 1 Imem_master_num;
+{0}
+typedef TAdd#(LastGen_master_num, `ifdef Debug 1 `else 0 `endif ) Debug_master_num;
+typedef TAdd#(Debug_master_num, `ifdef DMA 1 `else 0 `endif ) DMA_master_num;
+typedef TAdd#(DMA_master_num,1) Num_Masters;
+"""
+
+axi_fastslave_declarations = """\
+{0}
+typedef TAdd#(LastGen_fastslave_num,1) Sdram_cfg_slave_num;
+typedef TAdd#(Sdram_slave_num ,`ifdef SDRAM 1 `else 0 `endif ) Sdram_cfg_slave_num;
+typedef TAdd#(Sdram_cfg_slave_num,`ifdef BOOTROM 1 `else 0 `endif ) BootRom_slave_num ;
+typedef TAdd#(BootRom_slave_num ,`ifdef Debug 1 `else 0 `endif ) Debug_slave_num ;
+typedef TAdd#(Debug_slave_num , `ifdef TCMemory 1 `else 0 `endif ) TCM_slave_num;
+typedef TAdd#(TCM_slave_num ,`ifdef DMA 1 `else 0 `endif ) Dma_slave_num;
+typedef TAdd#(Dma_slave_num ,1 ) SlowPeripheral_slave_num;
+typedef TAdd#(SlowPeripheral_slave_num,`ifdef VME 1 `else 0 `endif ) VME_slave_num;
+typedef TAdd#(VME_slave_num,`ifdef FlexBus 1 `else 0 `endif ) FlexBus_slave_num;
+typedef TAdd#(FlexBus_slave_num,1) Num_Slaves;
+
+"""
axi_slave_declarations = """\
typedef 0 SlowMaster;
if slow:
self.slow = slow(ifacename)
self.slow.peripheral = self
- for fname in ['slowimport',
- 'slowifinstance', 'slowifdecl', 'slowifdeclmux',
- 'mkslow_peripheral', 'mk_plic', 'mk_ext_ifacedef',
+ for fname in ['slowimport',
+ 'extifinstance', 'extifdecl',
+ 'slowifdecl', 'slowifdeclmux',
+ 'mkslow_peripheral',
+ 'mkfast_peripheral',
+ 'mk_plic', 'mk_ext_ifacedef',
'mk_connection', 'mk_cellconn', 'mk_pincon']:
fn = CallFn(self, fname)
setattr(self, fname, types.MethodType(fn, self))
return ('', 0)
return self.slow.axi_reg_def(start, self.ifacename, count)
- def axi_slave_idx(self, start, count):
+ def axi_master_idx(self, start, count, typ):
+ if not self.slow or not self.slow.has_axi_master():
+ return ('', 0)
+ return self.slow.axi_master_idx(start, self.ifacename, count, typ)
+
+ def axi_slave_idx(self, start, count, typ):
if not self.slow:
return ('', 0)
- return self.slow.axi_slave_idx(start, self.ifacename, count)
+ return self.slow.axi_slave_idx(start, self.ifacename, count, typ)
def axi_addr_map(self, count):
if not self.slow:
class PeripheralInterfaces(object):
def __init__(self):
- pass
+ self.fastbusmode = False
def slowimport(self, *args):
ret = []
ret.append(self.data[name].slowimport())
return '\n'.join(list(filter(None, ret)))
- def slowifinstance(self, *args):
+ def extifinstance(self, *args):
ret = []
for (name, count) in self.ifacecount:
- #print "slowimport", name, self.data[name].slowimport
- ret.append(self.data[name].slowifinstance())
+ for i in range(count):
+ iname = self.data[name].iname().format(i)
+ if not self.is_on_fastbus(name, i):
+ continue
+ ret.append(self.data[name].extifinstance(name, i))
+ return '\n'.join(list(filter(None, ret)))
+
+ def extifdecl(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ if not self.is_on_fastbus(name, i):
+ continue
+ ret.append(self.data[name].extifdecl(name, i))
return '\n'.join(list(filter(None, ret)))
def slowifdeclmux(self, *args):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
- ret.append(self.data[name].slowifdeclmux().format(i, name))
+ ret.append(self.data[name].slowifdeclmux(name, i))
return '\n'.join(list(filter(None, ret)))
def slowifdecl(self, *args):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
ret.append(self.data[name].slowifdecl().format(i, name))
return '\n'.join(list(filter(None, ret)))
start = 0x00011100 # start of AXI peripherals address
for (name, count) in self.ifacecount:
for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
x = self.data[name].axi_reg_def(start, i)
#print ("ifc", name, x)
(rdef, offs) = x
start += offs
return '\n'.join(list(filter(None, ret)))
- def axi_slave_idx(self, *args):
+ def _axi_num_idx(self, start, template, typ, idxtype, *args):
ret = []
- start = 0
for (name, count) in self.ifacecount:
for i in range(count):
- (rdef, offs) = self.data[name].axi_slave_idx(start, i)
+ if self.is_on_fastbus(name, i):
+ continue
+ if typ == 'master':
+ fn = self.data[name].axi_master_idx
+ else:
+ fn = self.data[name].axi_slave_idx
+ (rdef, offs) = fn(start, i, idxtype)
#print ("ifc", name, rdef, offs)
ret.append(rdef)
start += offs
- ret.append("typedef %d LastGen_slave_num;" % (start - 1))
+ ret.append("typedef %d LastGen_%s_num;" % (start - 1, typ))
decls = '\n'.join(list(filter(None, ret)))
- return axi_slave_declarations.format(decls)
+ return template.format(decls)
+
+ def axi_slave_idx(self, *args):
+ return self._axi_num_idx(0, axi_slave_declarations, 'slave',
+ '', *args)
+
+ def axi_fastslave_idx(self, *args):
+ return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
+ 'fast', *args)
+
+ def axi_master_idx(self, *args):
+ return self._axi_num_idx(2, axi_master_declarations, 'master',
+ 'master', *args)
+
+ def axi_fastslave_idx(self, *args):
+ return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave',
+ 'fast', *args)
def axi_addr_map(self, *args):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
ret.append(self.data[name].axi_addr_map(i))
return '\n'.join(list(filter(None, ret)))
+ def mkfast_peripheral(self, *args):
+ ret = []
+ for (name, count) in self.ifacecount:
+ for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
+ #print "mkfast", name, count
+ x = self.data[name].mkfast_peripheral()
+ print name, count, x
+ suffix = self.data[name].mksuffix(name, i)
+ ret.append(x.format(suffix))
+ return '\n'.join(list(filter(None, ret)))
+
def mkslow_peripheral(self, *args):
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
- print "mkslow", name, count
+ if self.is_on_fastbus(name, i):
+ continue
+ #print "mkslow", name, count
x = self.data[name].mkslow_peripheral()
print name, count, x
suffix = self.data[name].mksuffix(name, i)
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
- print "mk_conn", name, i
+ if self.is_on_fastbus(name, i):
+ continue
txt = self.data[name].mk_connection(i)
if name == 'gpioa':
print "txt", txt
cellcount = 0
for (name, count) in self.ifacecount:
for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
res = self.data[name].mk_cellconn(cellcount, name, i)
if not res:
continue
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
txt = self.data[name].mk_pincon(name, i)
ret.append(txt)
return '\n'.join(list(filter(None, ret)))
ret = []
for (name, count) in self.ifacecount:
for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
txt = self.data[name].mk_ext_ifacedef(name, i)
ret.append(txt)
return '\n'.join(list(filter(None, ret)))
-
def mk_plic(self):
ret = []
- irq_offs = 8 # XXX: DMA scovers 0-7?
+ irq_offs = 8 # XXX: DMA scovers 0-7?
for (name, count) in self.ifacecount:
for i in range(count):
+ if self.is_on_fastbus(name, i):
+ continue
res = self.data[name].mk_plic(i, irq_offs)
if not res:
continue
def mk_sloirqsdef(self):
return " `define NUM_SLOW_IRQS {0}".format(self.num_slow_irqs)
+ def is_on_fastbus(self, name, i):
+ #print "fastbus mode", self.fastbusmode, name, i
+ iname = self.data[name].iname().format(i)
+ if self.fastbusmode:
+ return iname not in self.fastbus
+ return iname in self.fastbus
+
class PFactory(object):
def getcls(self, name):
from twi import twi
from eint import eint
from jtag import jtag
- from spi import spi
- from qspi import qspi
+ from spi import spi, mspi
+ from qspi import qspi, mqspi
from gpio import gpio
+ from rgbttl import rgbttl
for k, v in {'uart': uart,
'rs232': rs232,
'twi': twi,
'quart': quart,
+ 'mqspi': mqspi,
+ 'mspi': mspi,
'qspi': qspi,
'spi': spi,
'pwm': pwm,
'eint': eint,
'sd': sdmmc,
'jtag': jtag,
+ 'lcd': rgbttl,
'gpio': gpio
}.items():
if name.startswith(k):
return v
return None
+
slowfactory = PFactory()
if __name__ == '__main__':
projects / pinmux.git / blobdiff