AddingPeripherals.mdwn

[pinmux.git] / src / bsv / peripheral_gen / quart.py

diff --git a/src/bsv/peripheral_gen/quart.py b/src/bsv/peripheral_gen/quart.py
index 51e180389fb967ac190c4a9006587d74780b5a56..83fd81014c4cc41fe0735173dea5ae9b1b2954fe 100644 (file)
--- a/src/bsv/peripheral_gen/quart.py
+++ b/src/bsv/peripheral_gen/quart.py
@@ -4,44 +4,43 @@ from bsv.peripheral_gen.base import PBase
 class quart(PBase):
 
     def slowimport(self):
-        return "import Uart16550         :: *;"
+        return "import quart :: *;"
 
     def irq_name(self):
         return "quart{0}_intr"
 
     def slowifdecl(self):
-        return "interface RS232_PHY_Ifc quart{0}_coe;\n" + \
+        return "interface QUART_AXI4_Lite_Ifc quart{0};\n" + \
                "method Bit#(1) %s;" % self.irq_name()
 
     def get_clock_reset(self, name, count):
-        return "slow_clock,slow_reset" # XXX TODO: change to uart_clock/reset
+        return "uart_clock,uart_reset"
 
     def num_axi_regs32(self):
         return 8
 
     def mkslow_peripheral(self, size=0):
-        return "// XXX TODO: change to uart_clock/reset" + \
-               "Uart16550_AXI4_Lite_Ifc quart{0} <- \n" + \
-               "                mkUart16550(clocked_by sp_clock,\n" + \
-               "                    reset_by sp_reset, sp_clock, sp_reset);"
+        return "QUART_AXI4_Lite_Ifc quart{0} <- \n" + \
+               "                mkQUART(clocked_by uart_clock,\n" + \
+               "                    reset_by uart_reset, sp_clock, sp_reset);"
 
     def _mk_connection(self, name=None, count=0):
-        return "quart{0}.slave_axi_uart"
+        return "quart{0}.slave"
 
     def pinname_out(self, pname):
-        return {'tx': 'coe_rs232.stx_out',
-                'rts': 'coe_rs232.rts_out',
+        return {'tx': 'out.stx_out',
+                'rts': 'out.rts_out',
                 }.get(pname, '')
 
     def pinname_in(self, pname):
-        return {'rx': 'coe_rs232.srx_in',
-                'cts': 'coe_rs232.cts_in'
+        return {'rx': 'out.srx_in',
+                'cts': 'out.cts_in'
                 }.get(pname, '')
 
     def __disabled_mk_pincon(self, name, count):
         ret = [PBase.mk_pincon(self, name, count)]
         ret.append("rule con_%s%d_io_in;" % (name, count))
-        ret.append("    {0}{1}.coe_rs232.modem_input(".format(name, count))
+        ret.append("    {0}{1}.out.modem_input(".format(name, count))
         for idx, pname in enumerate(['rx', 'cts']):
             sname = self.peripheral.pname(pname).format(count)
             ps = "pinmux.peripheral_side.%s" % sname
@@ -77,7 +76,7 @@ class quart(PBase):
 uart_plic_template = """\
 // PLIC {0} synchronisation with irq {1}
 SyncBitIfc#(Bit#(1)) {0}_interrupt <-
-                            mkSyncBitToCC(sp_clock, uart_reset);
+                            mkSyncBitToCC(uart_clock, uart_reset);
 rule plic_synchronize_{0}_interrupt_{1};
      {0}_interrupt.send({0}.irq);
 endrule