fix(iomux): Fix port signal length (given mux size non-power of 2)

[pinmux.git] / src / bsv / peripheral_gen / uart.py

diff --git a/src/bsv/peripheral_gen/uart.py b/src/bsv/peripheral_gen/uart.py
index c757c83b754ec889053be0e8c5825ef1c8adbefc..953ed120edf59a36501ffcf200b4068ca34f2d92 100644 (file)
--- a/src/bsv/peripheral_gen/uart.py
+++ b/src/bsv/peripheral_gen/uart.py
@@ -1,21 +1,25 @@
 from bsv.peripheral_gen.base import PBase
 
+
 class uart(PBase):
 
     def slowimport(self):
-        return "    import Uart_bs         :: *;\n" + \
-               "    import RS232_modified::*;"
+        return "import Uart_bs         :: *;\n" + \
+               "import RS232_modified::*;"
 
     def slowifdecl(self):
-        return "            interface RS232 uart{0}_coe;\n" + \
-               "            method Bit#(1) uart{0}_intr;"
+        return "interface RS232 uart{0}_coe;\n" + \
+               "method Bit#(1) uart{0}_intr;"
 
     def num_axi_regs32(self):
         return 8
 
+    def get_clock_reset(self, name, count):
+        return "uart_clock,uart_reset"
+
     def mkslow_peripheral(self, size=0):
-        return "        Ifc_Uart_bs uart{0} <- \n" + \
-               "                mkUart_bs(clocked_by sp_clock,\n" + \
+        return "Ifc_Uart_bs uart{0} <- \n" + \
+               "            mkUart_bs(clocked_by uart_clock,\n" + \
                "                    reset_by uart_reset, sp_clock, sp_reset);"
 
     def _mk_connection(self, name=None, count=0):