fix horrible hack in gpio naming
[pinmux.git] / src / bsv / peripheral_gen.py
index 519ca60eaaec1caf942cc560638c02b2d9033eed..c71375299a6cbc0127a18f1d256541ba443828f2 100644 (file)
@@ -6,6 +6,12 @@ class PBase(object):
     def __init__(self, name):
         self.name = name
 
+    def slowifdeclmux(self):
+        return ''
+
+    def slowifdecl(self):
+        return ''
+
     def axibase(self, name, ifacenum):
         name = name.upper()
         return "%(name)s%(ifacenum)dBase" % locals()
@@ -58,19 +64,22 @@ class PBase(object):
             if typ == 'out' or typ == 'inout':
                 ret.append("    rule con_%s%d_%s_out;" % (name, count, pname))
                 fname = self.pinname_out(pname)
+                if not n.startswith('gpio'): # XXX EURGH! horrible hack
+                  n_ = "{0}{1}".format(n, count)
+                else:
+                  n_ = n
                 if fname:
                     if p.get('outen'):
                         ps_ = ps + '_out'
                     else:
                         ps_ = ps
-                    n_ = "{0}{1}".format(n, count)
                     ret.append("      {0}({1}.{2});".format(ps_, n_, fname))
                 fname = None
                 if p.get('outen'):
                     fname = self.pinname_outen(pname)
                 if fname:
                     if isinstance(fname, str):
-                        fname = "{0}{1}.{2}".format(n, count, fname)
+                        fname = "{0}.{1}".format(n_, fname)
                     fname = self.pinname_tweak(pname, 'outen', fname)
                     ret.append("      {0}_outen({1});".format(ps, fname))
                 ret.append("    endrule")
@@ -136,6 +145,34 @@ class PBase(object):
 
 class uart(PBase):
 
+    def slowimport(self):
+        return "          import Uart_bs         :: *;\n" + \
+               "          import RS232_modified::*;"
+
+    def slowifdecl(self):
+        return "            interface RS232 uart{0}_coe;\n" + \
+               "            method Bit#(1) uart{0}_intr;"
+
+    def num_axi_regs32(self):
+        return 8
+
+    def mkslow_peripheral(self, size=0):
+        return "        Ifc_Uart_bs uart{0} <- \n" + \
+               "                mkUart_bs(clocked_by sp_clock,\n" + \
+               "                    reset_by uart_reset, sp_clock, sp_reset);"
+
+    def _mk_connection(self, name=None, count=0):
+        return "uart{0}.slave_axi_uart"
+
+    def pinname_out(self, pname):
+        return {'tx': 'coe_rs232.sout'}.get(pname, '')
+
+    def pinname_in(self, pname):
+        return {'rx': 'coe_rs232.sin'}.get(pname, '')
+
+
+class qquart(PBase):
+
     def slowimport(self):
         return "          import Uart16550         :: *;"
 
@@ -148,7 +185,7 @@ class uart(PBase):
 
     def mkslow_peripheral(self, size=0):
         return "        Uart16550_AXI4_Lite_Ifc uart{0} <- \n" + \
-               "                mkUart16550(clocked_by uart_clock,\n" + \
+               "                mkUart16550(clocked_by sp_clock,\n" + \
                "                    reset_by uart_reset, sp_clock, sp_reset);"
 
     def _mk_connection(self, name=None, count=0):
@@ -294,16 +331,16 @@ class pwm(PBase):
         return "        import pwm::*;"
 
     def slowifdecl(self):
-        return "        interface PWMIO pwm{0}_o;"
+        return "        interface PWMIO pwm{0}_io;"
 
     def num_axi_regs32(self):
         return 4
 
     def mkslow_peripheral(self, size=0):
-        return "        Ifc_PWM_bus pwm{0}_bus <- mkPWM_bus(sp_clock);"
+        return "        Ifc_PWM_bus pwm{0} <- mkPWM_bus(sp_clock);"
 
     def _mk_connection(self, name=None, count=0):
-        return "pwm{0}_bus.axi4_slave"
+        return "pwm{0}.axi4_slave"
 
     def pinname_out(self, pname):
         return {'out': 'pwm_io.pwm_o'}.get(pname, '')
@@ -316,8 +353,9 @@ class gpio(PBase):
                "     import mux::*;\n" + \
                "     import gpio::*;\n"
 
-    def slowifdecl(self):
-        return "        interface GPIO_config#({1}) pad_config{0};"
+    def slowifdeclmux(self):
+        size = len(self.peripheral.pinspecs)
+        return "    interface GPIO_config#(%d) pad_config{0};" % size
 
     def num_axi_regs32(self):
         return 2
@@ -331,7 +369,7 @@ class gpio(PBase):
         mname = mname.upper()
         print "AXIslavenum", name,  mname
         (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum)
-        (ret2, x) = PBase.axi_slave_idx(self, idx, mname, ifacenum)
+        (ret2, x) = PBase.axi_slave_idx(self, idx+1, mname, ifacenum)
         return ("%s\n%s" % (ret, ret2), 2)
 
     def mkslow_peripheral(self, size=0):
@@ -373,8 +411,7 @@ class gpio(PBase):
         return "func.gpio_out[{0}]".format(pname[1:])
 
     def pinname_outen(self, pname):
-        return {'sda': 'out.sda_outen',
-                'scl': 'out.scl_outen'}.get(pname, '')
+        return "func.gpio_outen[{0}]".format(pname[1:])
 
     def mk_pincon(self, name, count):
         ret = [PBase.mk_pincon(self, name, count)]
@@ -434,7 +471,8 @@ class PeripheralIface(object):
         if slow:
             self.slow = slow(ifacename)
             self.slow.peripheral = self
-        for fname in ['slowimport', 'slowifdecl', 'mkslow_peripheral',
+        for fname in ['slowimport', 'slowifdecl', 'slowifdeclmux', 
+                      'mkslow_peripheral',
                       'mk_connection', 'mk_cellconn', 'mk_pincon']:
             fn = CallFn(self, fname)
             setattr(self, fname, types.MethodType(fn, self))
@@ -474,6 +512,13 @@ class PeripheralInterfaces(object):
             ret.append(self.data[name].slowimport())
         return '\n'.join(list(filter(None, ret)))
 
+    def slowifdeclmux(self, *args):
+        ret = []
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                ret.append(self.data[name].slowifdeclmux().format(i, name))
+        return '\n'.join(list(filter(None, ret)))
+
     def slowifdecl(self, *args):
         ret = []
         for (name, count) in self.ifacecount: