header = copyright + '''
package pinmux;
+import GetPut::*;
+import Vector::*;
+
'''
footer = '''
endmodule
shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
os.path.join(bp, 'Makefile'))
cwd = os.path.join(cwd, 'bsv_lib')
- for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
- 'gpio.bsv', 'mux.bsv',
- 'AXI4_Types.bsv', 'defined_types.bsv',
- 'AXI4_Fabric.bsv', 'Uart16550.bsv',
- 'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
- 'Uart_bs.bsv', 'RS232_modified.bsv',
- 'AXI4Lite_AXI4_Bridge.bsv',
- 'I2C_top.bsv', 'I2C_Defs.bsv',
- 'plic.bsv', 'Cur_Cycle.bsv',
- 'ClockDiv.bsv', 'axi_addr_generator.bsv',
- 'pwm.bsv', 'qspi.bsv', 'qspi.defs',
- ]:
+ for fname in []:
shutil.copyfile(os.path.join(cwd, fname),
os.path.join(bl, fname))
idef = os.path.join(bp, 'instance_defines.bsv')
slow = os.path.join(bp, 'slow_peripherals.bsv')
slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
+ soc = os.path.join(bp, 'soc.bsv')
+ soct = os.path.join(cwd, 'soc_template.bsv')
write_pmp(pmp, p, ifaces, iocells)
write_ptp(ptp, p, ifaces)
write_bus(bus, p, ifaces)
write_instances(idef, p, ifaces)
write_slow(slow, slowt, p, ifaces, iocells)
+ write_soc(soc, soct, p, ifaces, iocells)
-def write_slow(slow, template, p, ifaces, iocells):
+def write_slow(slow, slowt, p, ifaces, iocells):
""" write out the slow_peripherals.bsv file.
joins all the peripherals together into one AXI Lite interface
"""
- with open(template) as bsv_file:
- template = bsv_file.read()
+ with open(slowt) as bsv_file:
+ slowt = bsv_file.read()
imports = ifaces.slowimport()
- ifdecl = ifaces.slowifdecl()
+ ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
regdef = ifaces.axi_reg_def()
slavedecl = ifaces.axi_slave_idx()
fnaddrmap = ifaces.axi_addr_map()
mkcon = ifaces.mk_connection()
mkcellcon = ifaces.mk_cellconn()
pincon = ifaces.mk_pincon()
+ inst = ifaces.extifinstance()
+ mkplic = ifaces.mk_plic()
+ numsloirqs = ifaces.mk_sloirqsdef()
+ ifacedef = ifaces.mk_ext_ifacedef()
+ ifacedef = ifaces.mk_ext_ifacedef()
with open(slow, "w") as bsv_file:
- bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
- fnaddrmap, mkslow, mkcon, mkcellcon,
- pincon))
+ bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
+ fnaddrmap, mkslow, mkcon, mkcellcon,
+ pincon, inst, mkplic,
+ numsloirqs, ifacedef))
+
+def write_soc(soc, soct, p, ifaces, iocells):
+ """ write out the soc.bsv file.
+ joins all the peripherals together as AXI Masters
+ """
+ ifaces.fastbusmode = True # side-effects... shouldn't really do this
+ with open(soct) as bsv_file:
+ soct = bsv_file.read()
+ imports = ifaces.slowimport()
+ ifdecl = ifaces.fastifdecl()
+#ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
+ regdef = ifaces.axi_reg_def()
+ slavedecl = ifaces.axi_fastslave_idx()
+ mastdecl = ifaces.axi_master_idx()
+ fnaddrmap = ifaces.axi_addr_map()
+ mkfast = ifaces.mkfast_peripheral()
+ mkcon = ifaces.mk_fast_connection()
+ mkcellcon = ifaces.mk_cellconn()
+ pincon = ifaces.mk_pincon()
+ inst = ifaces.extfastifinstance()
+ mkplic = ifaces.mk_plic()
+ numsloirqs = ifaces.mk_sloirqsdef()
+ ifacedef = ifaces.mk_ext_ifacedef()
+ dma = ifaces.mk_dma_irq()
+ num_dmachannels = ifaces.num_dmachannels()
+ with open(soc, "w") as bsv_file:
+ bsv_file.write(soct.format(imports, ifdecl, mkfast,
+ slavedecl, mastdecl, mkcon,
+ inst, dma, num_dmachannels,
+ #'', '' #regdef, slavedecl,
+ #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
+ #pincon, inst, mkplic,
+ #numsloirqs, ifacedef))
+ ))
def write_bus(bus, p, ifaces):
cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
bsv_file.write('''\
- interface MuxSelectionLines;
+ (*always_ready,always_enabled*)
+ interface MuxSelectionLines;
// declare the method which will capture the user pin-mux
// selection values.The width of the input is dependent on the number
# ===== finish interface definition and start module definition=======
bsv_file.write("\n endinterface\n")
+ ifaces.ifacepfmt(bsv_file)
# ===== io cell definition =======
bsv_file.write('''
-
+ (*always_ready,always_enabled*)
interface PeripheralSide;
// declare the interface to the peripherals
// Each peripheral's function will be either an input, output
# ==============================================================
# == create method definitions for all peripheral interfaces ==#
- ifaces.ifacefmt(bsv_file)
+ ifaces.ifacefmt2(bsv_file)
bsv_file.write("\n endinterface\n")
# ===== finish interface definition and start module definition=======
// the I/O from the IOcell actually goes.
interface IOCellSide iocell_side;
endinterface
+
(*synthesize*)
module mkpinmux(Ifc_pinmux);
''')
bsv_file.write("\n endinterface;")
bsv_file.write('''
+
interface iocell_side = interface IOCellSide
''')
iocells.ifacedef(bsv_file)
bsv_file.write("\n endinterface;")
bsv_file.write('''
- interface peripheral_side = interface PeripheralSide
+
+ interface peripheral_side = interface PeripheralSide
''')
- ifaces.ifacedef(bsv_file)
- bsv_file.write("\n endinterface;")
+ ifaces.ifacedef2(bsv_file)
+ bsv_file.write("\n endinterface;")
bsv_file.write(footer)
print("BSV file successfully generated: bsv_src/pinmux.bsv")
`define USERSPACE 0
// TODO: work out if these are needed
-`define PWM_AXI4Lite
+`define PWM_AXI4Lite
`define PRFDEPTH 6
`define VADDR 39
`define DCACHE_BLOCK_SIZE 4
projects / pinmux.git / blobdiff