os.path.join(bp, 'Makefile'))
cwd = os.path.join(cwd, 'bsv_lib')
for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
- 'gpio.bsv', 'mux.bsv']:
+ 'gpio.bsv', 'mux.bsv',
+ 'AXI4_Types.bsv', 'defined_types.bsv',
+ 'AXI4_Fabric.bsv', 'Uart16550.bsv',
+ 'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
+ 'Uart_bs.bsv', 'RS232_modified.bsv',
+ 'AXI4Lite_AXI4_Bridge.bsv',
+ 'I2C_top.bsv', 'I2C_Defs.bsv',
+ 'plic.bsv', 'Cur_Cycle.bsv',
+ 'ClockDiv.bsv', 'axi_addr_generator.bsv',
+ 'jtagdtm_new.bsv', 'jtagdefines.bsv',
+ 'pwm.bsv', 'qspi.bsv', 'qspi.defs',
+ ]:
shutil.copyfile(os.path.join(cwd, fname),
os.path.join(bl, fname))
with open(template) as bsv_file:
template = bsv_file.read()
imports = ifaces.slowimport()
- ifdecl = ifaces.slowifdecl()
+ ifdecl = ifaces.slowifdeclmux()
regdef = ifaces.axi_reg_def()
slavedecl = ifaces.axi_slave_idx()
fnaddrmap = ifaces.axi_addr_map()
mkslow = ifaces.mkslow_peripheral()
mkcon = ifaces.mk_connection()
- mkcellcon = iocells.mk_cellconn()
+ mkcellcon = ifaces.mk_cellconn()
+ pincon = ifaces.mk_pincon()
with open(slow, "w") as bsv_file:
bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
- fnaddrmap, mkslow, mkcon, mkcellcon))
+ fnaddrmap, mkslow, mkcon, mkcellcon,
+ pincon))
def write_bus(bus, p, ifaces):
def write_instances(idef, p, ifaces):
with open(idef, 'w') as bsv_file:
txt = '''\
- `define ADDR {0}
- `define DATA {1}
- `define USERSPACE 0
+`define ADDR {0}
+`define PADDR {0}
+`define DATA {1}
+`define Reg_width {1}
+`define USERSPACE 0
+
+// TODO: work out if these are needed
+`define PWM_AXI4Lite
+`define PRFDEPTH 6
+`define VADDR 39
+`define DCACHE_BLOCK_SIZE 4
+`define DCACHE_WORD_SIZE 8
+`define PERFMONITORS 64
+`define DCACHE_WAYS 4
+`define DCACHE_TAG_BITS 20 // tag_bits = 52
+`define PLIC
+ `define PLICBase 'h0c000000
+ `define PLICEnd 'h10000000
+`define INTERRUPT_PINS 64
+
+`define BAUD_RATE 130
+`ifdef simulate
+ `define BAUD_RATE 5 //130 //
+`endif
'''
bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))