split out slow memory map to separate file

[pinmux.git] / src / bsv / pinmux_generator.py

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 485e1807e20c84b086ad1ab0178e17e0e20277e0..943f1675af65509a6a87cd25358a21b5bbdf6e93 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -86,7 +86,9 @@ def pinmuxgen(pth=None, verify=True):
     idef = os.path.join(bp, 'instance_defines.bsv')
     slow = os.path.join(bp, 'slow_peripherals.bsv')
     slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
-    soc = os.path.join(bp, 'soc.bsv')
+    slowmf = os.path.join(bp, 'slow_memory_map.bsv')
+    slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
+    soc = os.path.join(bp, 'socgen.bsv')
     soct = os.path.join(cwd, 'soc_template.bsv')
 
     write_pmp(pmp, p, ifaces, iocells)
@@ -94,14 +96,16 @@ def pinmuxgen(pth=None, verify=True):
     write_bvp(bvp, p, ifaces)
     write_bus(bus, p, ifaces)
     write_instances(idef, p, ifaces)
-    write_slow(slow, slowt, p, ifaces, iocells)
+    write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
     write_soc(soc, soct, p, ifaces, iocells)
 
 
-def write_slow(slow, slowt, p, ifaces, iocells):
+def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
     """ write out the slow_peripherals.bsv file.
         joins all the peripherals together into one AXI Lite interface
     """
+    with open(slowmt) as bsv_file:
+        slowmt = bsv_file.read()
     with open(slowt) as bsv_file:
         slowt = bsv_file.read()
     imports = ifaces.slowimport()
@@ -114,26 +118,34 @@ def write_slow(slow, slowt, p, ifaces, iocells):
     mkcellcon = ifaces.mk_cellconn()
     pincon = ifaces.mk_pincon()
     inst = ifaces.extifinstance()
+    inst2 = ifaces.extifinstance2()
     mkplic = ifaces.mk_plic()
     numsloirqs = ifaces.mk_sloirqsdef()
     ifacedef = ifaces.mk_ext_ifacedef()
     ifacedef = ifaces.mk_ext_ifacedef()
+
     with open(slow, "w") as bsv_file:
         bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
                                     fnaddrmap, mkslow, mkcon, mkcellcon,
                                     pincon, inst, mkplic,
-                                    numsloirqs, ifacedef))
+                                    numsloirqs, ifacedef,
+                                    inst2))
+
+    with open(slowmf, "w") as bsv_file:
+        bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
+
 
 def write_soc(soc, soct, p, ifaces, iocells):
     """ write out the soc.bsv file.
         joins all the peripherals together as AXI Masters
     """
-    ifaces.fastbusmode = True # side-effects... shouldn't really do this
+    ifaces.fastbusmode = True  # side-effects... shouldn't really do this
     with open(soct) as bsv_file:
         soct = bsv_file.read()
     imports = ifaces.slowimport()
-    ifdecl = "" #ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
-    regdef = ifaces.axi_reg_def()
+    ifdecl = ifaces.fastifdecl()
+#ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
+    regdef = ifaces.axi_fastmem_def()
     slavedecl = ifaces.axi_fastslave_idx()
     mastdecl = ifaces.axi_master_idx()
     fnaddrmap = ifaces.axi_addr_map()
@@ -141,19 +153,18 @@ def write_soc(soc, soct, p, ifaces, iocells):
     mkcon = ifaces.mk_fast_connection()
     mkcellcon = ifaces.mk_cellconn()
     pincon = ifaces.mk_pincon()
-    inst = ifaces.extifinstance()
+    inst = ifaces.extfastifinstance()
     mkplic = ifaces.mk_plic()
     numsloirqs = ifaces.mk_sloirqsdef()
     ifacedef = ifaces.mk_ext_ifacedef()
-    ifacedef = ifaces.mk_ext_ifacedef()
+    dma = ifaces.mk_dma_irq()
+    num_dmachannels = ifaces.num_dmachannels()
     with open(soc, "w") as bsv_file:
         bsv_file.write(soct.format(imports, ifdecl, mkfast,
-                            slavedecl, mastdecl, mkcon,
-                            #'', '' #regdef, slavedecl,
-                            #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
-                            #pincon, inst, mkplic,
-                            #numsloirqs, ifacedef))
-                                  ))
+                                   slavedecl, mastdecl, mkcon,
+                                   inst, dma, num_dmachannels,
+                                   pincon, regdef, fnaddrmap,
+                                   ))
 
 
 def write_bus(bus, p, ifaces):
@@ -428,6 +439,7 @@ def write_instances(idef, p, ifaces):
 `define DATA {1}
 `define Reg_width {1}
 `define USERSPACE 0
+`define RV64
 
 // TODO: work out if these are needed
 `define PWM_AXI4Lite
@@ -438,6 +450,11 @@ def write_instances(idef, p, ifaces):
 `define PERFMONITORS                            64
 `define DCACHE_WAYS 4
 `define DCACHE_TAG_BITS 20      // tag_bits = 52
+
+// CLINT
+    `define ClintBase       'h02000000
+    `define ClintEnd        'h020BFFFF
+
 `define PLIC
        `define PLICBase                'h0c000000
        `define PLICEnd         'h10000000