header = copyright + '''
package pinmux;
+import GetPut::*;
+import Vector::*;
+
'''
footer = '''
endmodule
# copy over template and library files
shutil.copyfile(os.path.join(cwd, 'Makefile.template'),
os.path.join(bp, 'Makefile'))
+ shutil.copyfile(os.path.join(cwd, 'Makefile.peripherals.template'),
+ os.path.join(bp, 'Makefile.peripherals'))
cwd = os.path.join(cwd, 'bsv_lib')
- for fname in ['AXI4_Lite_Types.bsv', 'Semi_FIFOF.bsv',
- 'gpio.bsv', 'mux.bsv',
- 'AXI4_Types.bsv', 'defined_types.bsv',
- 'AXI4_Fabric.bsv', 'Uart16550.bsv',
- 'AXI4_Lite_Fabric.bsv', 'ConcatReg.bsv',
- 'Uart_bs.bsv', 'RS232_modified.bsv',
- 'AXI4Lite_AXI4_Bridge.bsv',
- 'I2C_top.bsv', 'I2C_Defs.bsv',
- 'plic.bsv', 'Cur_Cycle.bsv',
- 'ClockDiv.bsv', 'axi_addr_generator.bsv',
- 'jtagdtm_new.bsv', 'jtagdefines.bsv',
- 'pwm.bsv', 'qspi.bsv', 'qspi.defs',
- ]:
+ for fname in []:
shutil.copyfile(os.path.join(cwd, fname),
os.path.join(bl, fname))
bus = os.path.join(bp, 'busenable.bsv')
pmp = os.path.join(bp, 'pinmux.bsv')
- ptp = os.path.join(bp, 'PinTop.bsv')
bvp = os.path.join(bp, 'bus.bsv')
idef = os.path.join(bp, 'instance_defines.bsv')
slow = os.path.join(bp, 'slow_peripherals.bsv')
slowt = os.path.join(cwd, 'slow_peripherals_template.bsv')
+ slowmf = os.path.join(bp, 'slow_memory_map.bsv')
+ slowmt = os.path.join(cwd, 'slow_tuple2_template.bsv')
+ fastmf = os.path.join(bp, 'fast_memory_map.bsv')
+ fastmt = os.path.join(cwd, 'fast_tuple2_template.bsv')
+ soc = os.path.join(bp, 'socgen.bsv')
+ soct = os.path.join(cwd, 'soc_template.bsv')
write_pmp(pmp, p, ifaces, iocells)
- write_ptp(ptp, p, ifaces)
write_bvp(bvp, p, ifaces)
write_bus(bus, p, ifaces)
write_instances(idef, p, ifaces)
- write_slow(slow, slowt, p, ifaces, iocells)
+ write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells)
+ write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells)
-def write_slow(slow, template, p, ifaces, iocells):
+def write_slow(slow, slowt, slowmf, slowmt, p, ifaces, iocells):
""" write out the slow_peripherals.bsv file.
joins all the peripherals together into one AXI Lite interface
"""
- with open(template) as bsv_file:
- template = bsv_file.read()
imports = ifaces.slowimport()
- ifdecl = ifaces.slowifdeclmux()
+ ifdecl = ifaces.slowifdeclmux() + '\n' + ifaces.extifdecl()
regdef = ifaces.axi_reg_def()
slavedecl = ifaces.axi_slave_idx()
fnaddrmap = ifaces.axi_addr_map()
mkcon = ifaces.mk_connection()
mkcellcon = ifaces.mk_cellconn()
pincon = ifaces.mk_pincon()
+ inst = ifaces.extifinstance()
+ inst2 = ifaces.extifinstance2()
+ mkplic = ifaces.mk_plic()
+ numsloirqs = ifaces.mk_sloirqsdef()
+ ifacedef = ifaces.mk_ext_ifacedef()
+ ifacedef = ifaces.mk_ext_ifacedef()
+ clockcon = ifaces.mk_slowclk_con()
+
with open(slow, "w") as bsv_file:
- bsv_file.write(template.format(imports, ifdecl, regdef, slavedecl,
- fnaddrmap, mkslow, mkcon, mkcellcon,
- pincon))
+ with open(slowt) as f:
+ slowt = f.read()
+ bsv_file.write(slowt.format(imports, ifdecl, regdef, slavedecl,
+ fnaddrmap, mkslow, mkcon, mkcellcon,
+ pincon, inst, mkplic,
+ numsloirqs, ifacedef,
+ inst2, clockcon))
+
+ with open(slowmf, "w") as bsv_file:
+ with open(slowmt) as f:
+ slowmt = f.read()
+ bsv_file.write(slowmt.format(regdef, slavedecl, fnaddrmap))
+
+
+def write_soc(soc, soct, fastmf, fastmt, p, ifaces, iocells):
+ """ write out the soc.bsv file.
+ joins all the peripherals together as AXI Masters
+ """
+ ifaces.fastbusmode = True # side-effects... shouldn't really do this
+
+ imports = ifaces.slowimport()
+ ifdecl = ifaces.fastifdecl()
+ regdef = ifaces.axi_fastmem_def()
+ slavedecl = ifaces.axi_fastslave_idx()
+ mastdecl = ifaces.axi_master_idx()
+ fnaddrmap = ifaces.axi_fastaddr_map()
+ mkfast = ifaces.mkfast_peripheral()
+ mkcon = ifaces.mk_fast_connection()
+ mkmstcon = ifaces.mk_master_connection()
+ mkcellcon = ifaces.mk_cellconn()
+ pincon = ifaces.mk_fast_pincon()
+ inst = ifaces.extfastifinstance()
+ mkplic = ifaces.mk_plic()
+ numsloirqs = ifaces.mk_sloirqsdef()
+ ifacedef = ifaces.mk_ext_ifacedef()
+ dma = ifaces.mk_dma_irq()
+ num_dmachannels = ifaces.num_dmachannels()
+ clockcon = ifaces.mk_fastclk_con()
+
+ with open(soc, "w") as bsv_file:
+ with open(soct) as f:
+ soct = f.read()
+ bsv_file.write(soct.format(imports, ifdecl, mkfast,
+ slavedecl, mastdecl, mkcon,
+ inst, dma, num_dmachannels,
+ pincon, regdef, fnaddrmap,
+ clockcon, mkmstcon,
+ ))
+
+ with open(fastmf, "w") as bsv_file:
+ with open(fastmt) as f:
+ fastmt = f.read()
+ bsv_file.write(fastmt.format(regdef, slavedecl, mastdecl, fnaddrmap))
def write_bus(bus, p, ifaces):
with open(pmp, "w") as bsv_file:
bsv_file.write(header)
- cell_bit_width = 'Bit#(%d)' % p.cell_bitwidth
+ bwid_template = 'Bit#(%d)'
bsv_file.write('''\
- interface MuxSelectionLines;
+ (*always_ready,always_enabled*)
+ interface MuxSelectionLines;
// declare the method which will capture the user pin-mux
// selection values.The width of the input is dependent on the number
// where each IO will have the same number of muxes.''')
for cell in p.muxed_cells:
- bsv_file.write(mux_interface.ifacefmt(cell[0], cell_bit_width))
+ cellnum = cell[0]
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
+ bsv_file.write(mux_interface.ifacefmt(cellnum, cell_bit_width))
bsv_file.write("\n endinterface\n")
# ===== finish interface definition and start module definition=======
bsv_file.write("\n endinterface\n")
+ ifaces.ifacepfmt(bsv_file)
# ===== io cell definition =======
bsv_file.write('''
-
+ (*always_ready,always_enabled*)
interface PeripheralSide;
// declare the interface to the peripherals
// Each peripheral's function will be either an input, output
# ==============================================================
# == create method definitions for all peripheral interfaces ==#
- ifaces.ifacefmt(bsv_file)
+ ifaces.ifacefmt2(bsv_file)
bsv_file.write("\n endinterface\n")
# ===== finish interface definition and start module definition=======
// the I/O from the IOcell actually goes.
interface IOCellSide iocell_side;
endinterface
+
(*synthesize*)
module mkpinmux(Ifc_pinmux);
''')
// values for each mux assigned to a CELL
''')
for cell in p.muxed_cells:
- bsv_file.write(mux_interface.wirefmt(
- cell[0], cell_bit_width))
+ cellnum = cell[0]
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
+ bsv_file.write(mux_interface.wirefmt(cellnum, cell_bit_width))
iocells.wirefmt(bsv_file)
ifaces.wirefmt(bsv_file)
bsv_file.write('''
/*====== This where the muxing starts for each io-cell======*/
Wire#(Bit#(1)) val0<-mkDWire(0); // need a zero
+ Wire#(Bit#(1)) val1<-mkDWire(1); // need a one
''')
bsv_file.write(p.pinmux)
bsv_file.write('''
interface mux_lines = interface MuxSelectionLines
''')
for cell in p.muxed_cells:
+ cellnum = cell[0]
+ bitwidth = p.get_muxbitwidth(cellnum)
+ if bitwidth == 0:
+ continue
+ cell_bit_width = bwid_template % bitwidth
bsv_file.write(
mux_interface.ifacedef(
- cell[0], cell_bit_width))
+ cellnum, cell_bit_width))
bsv_file.write("\n endinterface;")
bsv_file.write('''
+
interface iocell_side = interface IOCellSide
''')
iocells.ifacedef(bsv_file)
bsv_file.write("\n endinterface;")
bsv_file.write('''
- interface peripheral_side = interface PeripheralSide
+
+ interface peripheral_side = interface PeripheralSide
''')
- ifaces.ifacedef(bsv_file)
- bsv_file.write("\n endinterface;")
+ ifaces.ifacedef2(bsv_file)
+ bsv_file.write("\n endinterface;")
bsv_file.write(footer)
print("BSV file successfully generated: bsv_src/pinmux.bsv")
# ======================================================================
-def write_ptp(ptp, p, ifaces):
- with open(ptp, 'w') as bsv_file:
- bsv_file.write(copyright + '''
-package PinTop;
- import pinmux::*;
- interface Ifc_PintTop;
- method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
- method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
- interface PeripheralSide peripheral_side;
- endinterface
-
- module mkPinTop(Ifc_PintTop);
- // instantiate the pin-mux module here
- Ifc_pinmux pinmux <-mkpinmux;
-
- // declare the registers which will be used to mux the IOs
-'''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
-
- cell_bit_width = str(p.cell_bitwidth)
- for cell in p.muxed_cells:
- bsv_file.write('''
- Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
- cell_bit_width, cell[0]))
-
- bsv_file.write('''
- // rule to connect the registers to the selection lines of the
- // pin-mux module
- rule connect_selection_registers;''')
-
- for cell in p.muxed_cells:
- bsv_file.write('''
- pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
-
- bsv_file.write('''
- endrule
- // method definitions for the write user interface
- method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
- Bool err=False;
- case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
- p.ADDR_WIDTH, p.DATA_WIDTH))
- index = 0
- for cell in p.muxed_cells:
- bsv_file.write('''
- {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
- index = index + 1
-
- bsv_file.write('''
- default: err=True;
- endcase
- return err;
- endmethod''')
-
- bsv_file.write('''
- // method definitions for the read user interface
- method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
- Bool err=False;
- Bit#(32) data=0;
- case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
- p.ADDR_WIDTH, p.DATA_WIDTH))
- index = 0
- for cell in p.muxed_cells:
- bsv_file.write('''
- {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
- index = index + 1
-
- bsv_file.write('''
- default:err=True;
- endcase
- return tuple2(err,data);
- endmethod
- interface peripheral_side=pinmux.peripheral_side;
- endmodule
-endpackage
-''')
-
-
def write_bvp(bvp, p, ifaces):
# ######## Generate bus transactors ################
gpiocfg = '\t\tinterface GPIO_config#({4}) bank{3}_config;\n' \
with open(idef, 'w') as bsv_file:
txt = '''\
`define ADDR {0}
-`define PADDR {0}
+`define PADDR {2}
`define DATA {1}
`define Reg_width {1}
`define USERSPACE 0
+`define RV64
// TODO: work out if these are needed
-`define PWM_AXI4Lite
+`define PWM_AXI4Lite
`define PRFDEPTH 6
`define VADDR 39
`define DCACHE_BLOCK_SIZE 4
`define PERFMONITORS 64
`define DCACHE_WAYS 4
`define DCACHE_TAG_BITS 20 // tag_bits = 52
+
+// CLINT
+ `define ClintBase 'h02000000
+ `define ClintEnd 'h020BFFFF
+
`define PLIC
`define PLICBase 'h0c000000
`define PLICEnd 'h10000000
`define BAUD_RATE 5 //130 //
`endif
'''
- bsv_file.write(txt.format(p.ADDR_WIDTH, p.DATA_WIDTH))
+ bsv_file.write(txt.format(p.ADDR_WIDTH,
+ p.DATA_WIDTH,
+ p.PADDR_WIDTH))