set dram_clk_freq to None

[ls2.git] / src / ls2.py

diff --git a/src/ls2.py b/src/ls2.py
index 283eb410e7c16bb924001255f8618f15cba6f205..0e72d473740a531f529bfc4e4313fda446f79ff5 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -547,6 +547,7 @@ class DDR3SoC(SoC, Elaboratable):
         if spi_0_pins is not None and fpga in ['sim',
                                              'isim',
                                              'rcs_arctic_tern_bmc_card',
+                                             'orangecrab',
                                              'versa_ecp5',
                                              'versa_ecp5_85',
                                              'arty_a7']:
@@ -557,6 +558,7 @@ class DDR3SoC(SoC, Elaboratable):
             if fpga in ['versa_ecp5',
                         'versa_ecp5_85',
                         'rcs_arctic_tern_bmc_card',
+                        'orangecrab',
                         'isim']:
                 spi0_is_lattice_ecp5_clk = True
 
@@ -795,8 +797,8 @@ class DDR3SoC(SoC, Elaboratable):
         # and at the moment that's just UART tx/rx.
         ports = []
         ports += [self.uart.tx_o, self.uart.rx_i]
-        if hasattr(self, "hyperram"):
-            ports += list(self.hyperram.ports())
+        for hr in self.hyperram:
+            ports += list(hr.ports())
         if hasattr(self, "ddrphy"):
             if hasattr(self.ddrphy, "pads"): # real PHY
                 ports += list(self.ddrphy.pads.fields.values())
@@ -835,6 +837,7 @@ def build_platform(fpga, firmware):
     dram_cls = {'arty_a7': None,
                  'versa_ecp5': MT41K64M16,
                  'versa_ecp5_85': MT41K64M16,
+                 'orangecrab': MT41K64M16,
                  #'versa_ecp5': MT41K256M16,
                  'ulx3s': None,
                  'sim': MT41K256M16,
@@ -868,7 +871,7 @@ def build_platform(fpga, firmware):
         clk_freq = 50e6
         dram_clk_freq = 100e6
     if fpga == 'arty_a7':
-        clk_freq = 50e6
+        clk_freq = 27.0e6 # urrr "working" with the QSPI core (25 mhz does not)
     if fpga == 'ulx3s':
         clk_freq = 40.0e6
     if fpga == 'orangecrab':
@@ -896,7 +899,7 @@ def build_platform(fpga, firmware):
     if platform is not None:
         if fpga=="orangecrab":
             # assumes an FT232 USB-UART soldered onto these two pins.
-            orangecrab_uart = UARTResource(0, rx="N17", tx="M18")
+            orangecrab_uart = UARTResource(0, rx="M18", tx="N17")
             platform.add_resources([orangecrab_uart])
 
         uart_pins = platform.request("uart", 0)
@@ -906,7 +909,8 @@ def build_platform(fpga, firmware):
     # get DDR resource pins, disable if clock frequency is below 50 mhz for now
     ddr_pins = None
     if (enable_dram and platform is not None and
-        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim']): # not yet 'arty_a7',
+        fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim',
+                 'orangecrab']): # not yet 'arty_a7',
         ddr_pins = platform.request("ddr3", 0,
                                     dir={"dq":"-", "dqs":"-"},
                                     xdr={"rst": 4, "clk":4, "a":4,
@@ -953,6 +957,33 @@ def build_platform(fpga, firmware):
         platform.add_resources(spi_0_ios)
         spi_0_pins = platform.request("spi_0", 0)
 
+
+    if platform is not None and \
+       fpga in ['orangecrab']:
+       # spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
+       # spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
+       # spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
+       # spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
+       # cs_n="U17", clk="U16", miso="T18", mosi="U18", wp_n="R18", hold_n="N18"
+        # each pin needs a separate direction control
+        spi_0_ios = [
+            Resource("spi_0", 0,
+                     Subsignal("dq0",  Pins("U18", dir="io")), #mosi
+                     Subsignal("dq1",  Pins("T18", dir="io")), #miso
+                     Subsignal("dq2",  Pins("R18", dir="io")), #wp_n
+                     Subsignal("dq3",  Pins("N18", dir="io")), #hold_n
+                     # We use USRMCLK instead for clk
+                     # todo: read docs
+                     Subsignal("cs_n", Pins("U17", dir="o")),
+                     # Subsignal("clk",  Pins("U16", dir="o")),
+                     Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33"))
+        ]
+        platform.add_resources(spi_0_ios)
+        spi_0_pins = platform.request("spi_0", 0, dir={"cs_n":"o"},
+                                                  xdr={"dq0":1, "dq1": 1,
+                                                       "dq2":1, "dq3": 1,
+                                                       "cs_n":0})
+
     print ("spiflash pins", spi_0_pins)
 
     # Get Ethernet RMII resource pins
@@ -1072,6 +1103,12 @@ def build_platform(fpga, firmware):
         #os.environ['NMIGEN_synth_opts'] = '-abc9'
         os.environ['NMIGEN_synth_opts'] = '-nowidelut'
 
+    if toolchain == 'yosys_nextpnr':
+        # add --seed 2 to arty a7 compile-time options
+        freq = clk_freq/1e6
+        os.environ['NMIGEN_nextpnr_opts'] = '--seed 3 --freq %.1f' % freq
+        os.environ['NMIGEN_nextpnr_opts'] += ' --timing-allow-fail'
+
     if platform is not None:
         # build and upload it
         if fpga == 'isim':